Atish Patra [Tue, 7 May 2019 00:49:39 +0000 (17:49 -0700)]
RISCV: image: Add booti support
This patch adds booti support for RISC-V Linux kernel. The existing
bootm method will also continue to work as it is.
It depends on the following kernel patch which adds the header to the
flat Image. Gzip compressed Image (Image.gz) support is not enabled with
this patch.
Rick Chen [Tue, 30 Apr 2019 05:49:33 +0000 (13:49 +0800)]
riscv: Introduce CONFIG_XIP to support booting from flash
When U-Boot boots from flash, during the boot process,
hart_lottery and available_harts_lock variable addresses
point to flash which is not writable. This causes boot
failures on AE350. Introduce a config option CONFIG_XIP
to support such configuration.
Signed-off-by: Rick Chen <rick@andestech.com> Cc: Greentime Hu <greentime@andestech.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
riscv: qemu: Use correct SYS_TEXT_BASE for S-mode on 32bit system
For 32bit system, the OpenSBI (or BBL) will jump to 0x80400000 address
in S-mode whereas for 64bit system it will jump to 0x80200000 address
in S-mode.
Currently, the S-mode U-Boot sets SYS_TEXT_BASE to 0x80200000 for both
32bit and 64bit system. This breaks S-mode U-Boot for 32bit system.
This patch sets different SYS_TEXT_BASE for 32bit and 64bit system so
that S-mode U-Boot works fine for both.
After updating Fedora/RISCV kernel to 5.1-rc3+ the size increased above
the current threshold. Looking into HiKey, Dragonboards, etc. seems that
SZ_64M is a popular option.
This sucessfully boots Fedora/RISCV with 5.1-rc3+ kernel on QEMU 4.0 (master)
with OpenSBI -> U-Boot (S-mode) [extlinux] -> Kernel setup.
Signed-off-by: David Abdurachmanov <david.abdurachmanov@gmail.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Neil Armstrong [Tue, 19 Feb 2019 13:21:04 +0000 (14:21 +0100)]
mach-meson: g12a: add DWC2 peripheral mode support
Adds support for Amlogic G12A USB Device mode.
The DWC2 Controller behind the Glue can be connected to an OTG
capable PHY. The Glue setups the PHY mode.
This patch implements Device mode support by adding a board_usb_init/cleanup
setting up the DWC2 controller and switch the OTG capable port to Device
before starting the DWC2 controller in Device mode.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Neil Armstrong [Tue, 19 Feb 2019 14:17:29 +0000 (15:17 +0100)]
phy: meson: add Amlogic G12A USB2 and USB3+PCIE PHY drivers
This adds support for the USB PHYs found in the Amlogic G12A SoC Family.
The USB2 PHY supports Host and/or Peripheral mode, depending on it's position.
The first PHY is only used as Host, but the second supports Dual modes
defined by the USB Control Glue HW in front of the USB Controllers.
The second driver supports USB3 Host mode or PCIE 2.0 mode, depending on
the layout of the board.
Selection is done by the #phy-cells, making the mode static and exclusive.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Neil Armstrong [Tue, 19 Feb 2019 12:42:01 +0000 (13:42 +0100)]
usb: dwc3: Add Meson G12A USB Glue
Adds support for Amlogic G12A USB Control Glue HW.
The Amlogic G12A SoC Family embeds 2 USB Controllers :
- a DWC3 IP configured as Host for USB2 and USB3
- a DWC2 IP configured as Peripheral USB2 Only
A glue connects these both controllers to 2 USB2 PHYs, and optionnally
to an USB3+PCIE Combo PHY shared with the PCIE controller.
The Glue configures the UTMI 8bit interfaces for the USB2 PHYs, including
routing of the OTG PHY between the DWC3 and DWC2 controllers, and
setups the on-chip OTG mode selection for this PHY.
This driver sets the OTG capable port as Host mode by default,
the switch to Device mode is to be done in a separate patch.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Marek Vasut <marex@denx.de>
James Byrne [Mon, 4 Mar 2019 17:40:34 +0000 (17:40 +0000)]
net: phy: micrel: Find Micrel PHY node correctly
In some of the device trees that specify skew values for KSZ90x1 PHYs
the values are stored (incorrectly) in the MAC node, whereas in others
it is in an 'ethernet-phy' subnode. Previously the code would fail to
find and program these skew values, so this commit changes it to look
for an "ethernet-phy" subnode first, and revert to looking in the MAC
node if there isn't one.
The device trees affected (where the skew values are in a subnode) are
imx6qdl-icore-rqs.dtsi, r8a77970-eagle.dts, r8a77990-ebisu.dts,
r8a77995-draak.dts, salvator-common.dtsi, sama5d3xcm.dtsi,
sama5d3xcm_cmp.dtsi, socfpga_cyclone5_vining_fpga.dts,
socfpga_stratix10_socdk.dts and ulcb.dtsi. Before this change the skew
values in these device trees would be ignored.
The device trees where the skew values are in the MAC node are
socfpga_arria10_socdk.dtsi, socfpga_arria5_socdk.dts,
socfpga_cyclone5_de0_nano_soc.dts, socfpga_cyclone5_de10_nano.dts,
socfpga_cyclone5_de1_soc.dts, socfpga_cyclone5_is1.dts,
socfpga_cyclone5_socdk.dts, socfpga_cyclone5_sockit.dts. These should be
unaffected by this change.
The changes were tested on a sama5d3xcm.
Signed-off-by: James Byrne <james.byrne@origamienergy.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
James Byrne [Mon, 4 Mar 2019 17:40:33 +0000 (17:40 +0000)]
net: phy: micrel: Use correct skew values on KSZ9021
Commit ff7bd212cb8a ("net: phy: micrel: fix divisor value for KSZ9031
phy skew") fixed the skew value divisor for the KSZ9031, but left the
code using the same divisor for the KSZ9021, which is incorrect.
The preceding commit c16e69f702b1 ("net: phy: micrel: add documentation
for Micrel KSZ90x1 binding") added the DTS documentation for the
KSZ90x1, changing it from the equivalent file in the Linux kernel to
correctly state that for this part the skew value is set in 120ps steps,
whereas the Linux documentation and driver continue to this day to use
the incorrect value of 200 that came from the original KSZ9021 datasheet
before it was corrected in revision 1.2 (Feb 2014).
This commit sorts out the resulting confusion in a consistent way by
making the following changes:
- Update the documentation to be clear about what the skew values mean,
in the same was as for the KSZ9031.
- Update the Micrel PHY driver to select the appropriate divisor for
both parts.
- Adjust all the device trees that state skew values for KSZ9021 PHYs to
use values based on 120ps steps instead of 200ps steps. This will result
in the same values being programmed into the skew registers as the
equivalent device trees in the Linux kernel do, where it incorrectly
uses 200ps steps (since that's where all these device trees were copied
from).
Signed-off-by: James Byrne <james.byrne@origamienergy.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
net: phy: aquantia: Set only autoneg on in register 4.c441
For AQR405 in register 4.c441 bit 15 was override with 0. This caused the
phy to not negotiate at 2.5GB rate with mac. To avoid
this override it needed first to know the previous value of reg 4.c441
and set only bit 3.
Signed-off-by: Valentin Catalin Neacsu <valentin-catalin.neacsu@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
net: phy: Reloc next and prev pointers inside phy_drivers
This patch relocates the pointers inside phy_drivers incase
of manual reloc. Without this reloc, these points to invalid
pre relocation address and hence causes exception or hang.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Murali Karicheri [Mon, 25 Feb 2019 20:27:34 +0000 (15:27 -0500)]
ARM: k2g-ice: Add pinmux support for rgmii interface
This add pinmux configuration for rgmii interface so that network
driver can be supported on K2G ICE boards. The pinmux configurations
for this are generated using the pinmux tool at
https://dev.ti.com/pinmux/app.html#/default
As this required some BUFFER_CLASS definitions, same is re-used
from the linux defnitions in include/dt-bindings/pinctrl/keystone.h
Chen-Yu Tsai [Fri, 3 May 2019 02:27:41 +0000 (10:27 +0800)]
sunxi: Enable EMAC on the Bananapi M3
The Bananapi M3 has an RTL8211E PHY connected to the EMAC using
RGMII. The PHY is powered by DCDC1 through SW @ 3.3V.
The board is designed to use 3.3V with RGMII, instead of the standard
reduced voltage of 2.5V we see everywhere. DLDO3, which provides the
I/O voltages, is raised to match.
This patch enables the EMAC and Realtek PHY drivers in the defconfig.
The device tree file already has the EMAC enabled.
Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Chen-Yu Tsai [Fri, 3 May 2019 02:27:40 +0000 (10:27 +0800)]
sunxi: Enable EMAC on the Cubietruck Plus
The Cubietruck Plus has an RTL8211E PHY connected to the EMAC using
RGMII. The PHY is powered by DLDO4 @ 3.3V, while the I/O pins are
powered by DLDO3 @ 2.5V.
This patch enables the EMAC and Realtek PHY drivers in the defconfig.
The device tree file already has the EMAC enabled.
Signed-off-by: Chen-Yu Tsai <wens@csie.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
Known broken:
- Internal keyboard (seems to be because the keyboard firmware loads a
bootloader first, and then disconnects bootloader and connect real
keyboard). External ones connected to the USB port work fine.
This patch enables support for the A64-Teres-I board to u-boot,
including enabling screen backlight (lacking from Linux device-tree).
Linux commit details about the sun50i-a64-teres-i.dts sync:
"arm64: dts: allwinner: a64: Rename uart0_pins_a label to uart0_pb_pins"
(sha1: d91ebb95b96c8840932dc3a10c9f243712555467)
Cosmetic warnings regarding whitespace and placement of SPDX notice for
dts file was ignored.
config and .dtsi file are adapted from pinebook files.
Tested-by: Jonas Smedegaard <dr@jones.dk> Signed-off-by: Jonas Smedegaard <dr@jones.dk> Signed-off-by: Icenowy Zheng <icenowy@aosc.io> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
[jagan: move board entry in MAINTAINERS file at proper position] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Jagan Teki [Wed, 27 Feb 2019 18:56:55 +0000 (00:26 +0530)]
reset: Get the RESET by index without device
Getting a RESET by index with device is not straight forward
for some use-cases like handling clock operations for child
node in parent driver. So we need to process the child node
in parent probe via ofnode and process RESET operation for child
without udevice but with ofnode.
So add reset_get_by_index_nodev() and move the common code
in reset_get_by_index_tail() to use for reset_get_by_index()
Cc: Stephen Warren <swarren@nvidia.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Jagan Teki [Wed, 27 Feb 2019 18:56:52 +0000 (00:26 +0530)]
clk: Get the CLK by index without device
Getting a CLK by index with device is not straight forward
for some use-cases like handling clock operations for child
node in parent driver. So we need to process the child node
in parent probe via ofnode and process CLK operation for child
without udevice but with ofnode.
So add clk_get_by_index_nodev() and move the common code
in clk_get_by_index_tail() to use for clk_get_by_index()
Cc: Stephen Warren <swarren@nvidia.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Jagan Teki [Wed, 8 May 2019 14:26:16 +0000 (19:56 +0530)]
serial: sifive: Change include order
Like clk_get_by_index, there is requirement for
clk_get_by_index_nodev. In this case to make common
code functionalities for dev and nodev, clk_get_by_index
is trying to get the index of clock by passing ofnode
instead of actual dev like current gpio uclass does.
In these scenarios with current order of include files
the serial_sifive driver is unable to find CONFIG_ENV_SIZE.
In file included from arch/riscv/include/asm/u-boot.h:23:0,
from include/dm/of.h:10,
from include/dm/ofnode.h:12,
from include/clk.h:11,
from drivers/serial/serial_sifive.c:6:
include/environment.h:145:19: error: 'CONFIG_ENV_SIZE'
undeclared here (not in a function); did you mean 'CONFIG_CMD_XIMG'?
#define ENV_SIZE (CONFIG_ENV_SIZE - ENV_HEADER_SIZE)
So, fix consists of changing the order of include files
in serial_sifive.c to include first common.h file.
Cc: Anup Patel <Anup.Patel@wdc.com> Cc: Rick Chen <rick@andestech.com> Cc: Paul Walmsley <paul.walmsley@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Jagan Teki [Wed, 8 May 2019 14:22:18 +0000 (19:52 +0530)]
clk: sifive: fu540-prci: Change include order
Like clk_get_by_index, there is requirement for
clk_get_by_index_nodev. In this case to make common
code functionalities for dev and nodev, clk_get_by_index
is trying to get the index of clock by passing ofnode
instead of actual dev like current gpio uclass does.
In these scenarios with current order of include files
the fu540-prci driver is unable to find CONFIG_ENV_SIZE.
In file included from arch/riscv/include/asm/u-boot.h:23:0,
from include/dm/of.h:10,
from include/dm/ofnode.h:12,
from include/clk.h:11,
from include/clk-uclass.h:13,
from drivers/clk/sifive/fu540-prci.c:32:
include/environment.h:145:19: error: 'CONFIG_ENV_SIZE'
undeclared here (not in a function); did you mean 'CONFIG_CMD_XIMG'?
#define ENV_SIZE (CONFIG_ENV_SIZE - ENV_HEADER_SIZE)
So, fix consists of changing the order of include files
in fu540-prci.c to include first common.h file.
Cc: Anup Patel <Anup.Patel@wdc.com> Cc: Rick Chen <rick@andestech.com> Cc: Paul Walmsley <paul.walmsley@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Jagan Teki [Wed, 8 May 2019 14:12:16 +0000 (19:42 +0530)]
spi: atcspi200: Change include order
Like clk_get_by_index, there is requirement for
clk_get_by_index_nodev. In this case to make common
code functionalities for dev and nodev, clk_get_by_index
is trying to get the index of clock by passing ofnode
instead of actual dev like current gpio uclass does.
In these scenarios with current order of include files
the atcspi200_spi driver is unable to find CONFIG_ENV_SIZE.
In file included from arch/nds32/include/asm/u-boot.h:24,
from include/dm/of.h:10,
from include/dm/ofnode.h:12,
from include/clk.h:11,
from drivers/spi/atcspi200_spi.c:9:
include/environment.h:145:19: error: 'CONFIG_ENV_SIZE'
undeclared here (not in a function); did you mean 'CONFIG_CMD_XIMG'?
#define ENV_SIZE (CONFIG_ENV_SIZE - ENV_HEADER_SIZE)
So, fix consists of changing the order of include files
in atcspi200_spi.c to include first common.h file.
Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Tom Rini [Wed, 8 May 2019 13:20:19 +0000 (09:20 -0400)]
Merge git://git.denx.de/u-boot-x86
- Allow x86 boards to use TPL, SPL and U-Boot proper
- Update sysreset x86 driver to utilize ACPI registers to do power off
- Add a new chromebook_samus_tpl board for TPL support
- Several minor changes in binman tool
Simon Glass [Wed, 8 May 2019 03:41:16 +0000 (21:41 -0600)]
x86: samus: Add a target to boot through TPL
Add a version of samus which supports booting from TPL to SPL and then
to U-Boot. This allows TPL to select from an A or B SPL to support
verified boot with field upgrade.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 2 May 2019 16:52:20 +0000 (10:52 -0600)]
x86: Update device tree for Chromium OS verified boot
The standard image generated by U-Boot on x86 is u-boot.rom. Add a
separate image called image.bin for verified boot. This supports
verification in TPL of which SPL/U-Boot to start, then jumping to the
correct one, with SPL setting up the SDRAM and U-Boot proper providing
the user interface if needed.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 2 May 2019 16:52:19 +0000 (10:52 -0600)]
x86: Update device tree for TPL
Add TPL binaries to the device x86 binman desciption. When enabled, TPL
will start first, doing the 16-bit init, then jump to SPL and finally
U-Boot proper.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 2 May 2019 16:52:16 +0000 (10:52 -0600)]
x86: Add documentation on the samus flashmap
There are quite a few variables which control where things appear in the
final ROM image. Add a flashmap in the documentation to make this easier
to figure out.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: squashed "x86: Update the memory map a little" in]
[bmeng: fixed typo of 'documentation' in the commit title] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Fri, 26 Apr 2019 03:59:08 +0000 (21:59 -0600)]
x86: Support PCI VGA ROM when TPL is used
When TPL is in use, U-Boot proper should support initing the VGA ROM even
though the 32-bit init portion is in SPL. Update the condition to handle
this.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 2 May 2019 16:52:15 +0000 (10:52 -0600)]
x86: sysreset: Implement the get_last() method
Add a default implementation of this method which always indicates that
the last reset was a power-on reset. This is the most likely type of reset
and without a PCH-specific driver we cannot determine any other type.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Thu, 2 May 2019 16:52:13 +0000 (10:52 -0600)]
x86: sysreset: Separate out the EFI code
The EFI implementation of reset sits inside the driver and is called
directly from outside the driver, breaking the normal driver-model
conventions. Worse, it passed NULL as the device pointer, hoping that
the called function won't use it, which breaks as soon as code is added
to use it.
Separate out the implementation to improve the situation enough to allow
a future patch to add new sysreset features.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Fri, 26 Apr 2019 03:58:57 +0000 (21:58 -0600)]
x86: Support saving MRC data from SPL
When SPL is used to set up the memory controller we want to save the MRC
data in SPL to avoid needing to pass it up to U-Boot proper to save. Add a
function to handle that.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Fri, 26 Apr 2019 03:58:54 +0000 (21:58 -0600)]
x86: broadwell: Allow booting from SPL
At present broadwell only supports booting straight into U-Boot proper.
Add a separate init file to boot from SPL into U-Boot proper, and select
it when SPL is in use.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Fri, 26 Apr 2019 03:58:51 +0000 (21:58 -0600)]
x86: broadwell: Split CPU init
Split the CPU init into two parts - the 'full' init which happens in the
first U-Boot phase, and the rest of the init that happens on subsequent
stages.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Fri, 26 Apr 2019 03:58:50 +0000 (21:58 -0600)]
x86: broadwell: Move init of debug UART to cpu.c
At present the debug UART is set up in sdram.c which is not the best place
since it has nothing in particular to do with SDRAM. Since we want to
support initing this in SPL too, move it to a common file.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
[bmeng: added 'broadwell' tag in the commit title] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Fri, 26 Apr 2019 03:58:49 +0000 (21:58 -0600)]
x86: broadwell: Allow SDRAM init from SPL
At present, for broadwell, SDRAM is always set up in U-Boot proper since
the 64-bit mode (which uses SDRAM init in SPL) is not supported.
Update the code to allow SDRAM init in SPL instead so that U-Boot proper
can be loaded into SDRAM and run from there. This allows U-Boot to be
compressed to reduce space, since it is not necessary to run it directly
from flash. It could later allow us to support 64-bit U-Boot on broadwell.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Fri, 26 Apr 2019 03:58:46 +0000 (21:58 -0600)]
x86: Support booting with TPL
Some boards want to use TPL as the first phase of U-Boot. This allows
selection of A or B SPL phases, thus allowing the memory init to be
upgraded in the field.
Add a new Kconfig option for this.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Fri, 26 Apr 2019 03:58:42 +0000 (21:58 -0600)]
x86: Add a way to reinit the cpu
We cannot init the CPU fully both than once during a boot. Add a new
function which can be called to figure out the CPU identity, but which
does not change anything. For x86_64, this is empty for now.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Unfortunately this has a dramatic impact on the pre-relocation memory
used on x86 platforms (increasing it by 2KB) since it increases the
overhead for each PCI device from 220 bytes to 412 bytes.
This means that all PCI devices have the controller struct associated
with them. The solution is to move the regions[] member out of the array,
makes its size dynamic, or split UCLASS_PCI into controllers and
non-controllers, as the comment suggests.
For now, revert the commit to get things running again.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Fri, 26 Apr 2019 03:58:38 +0000 (21:58 -0600)]
spl: Allow sandbox to build a device-tree file
At present only OF_SEPARATE is considered valid for building a device-tree
file in SPL. However sandbox uses OF_HOSTFILE instead. Update the logic to
handle this and make it easier to understand.
Note that the new logic is not quite the same as the old logic. It was
previously assumed that checking for:
producing 'yy' meant that the first two were 'y' and the last was empty.
Strictly speaking it would be possible for any two of the three to be 'y'
and still yield the same result. However, that was not the intention of
the new logic, since OF_PLATDATA always ensures that no device-tree file
is included. So in effect the new logic is the same, with the addition of
OF_HOSTFILE as an option for OP_SEPARATE.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Fri, 26 Apr 2019 03:58:39 +0000 (21:58 -0600)]
binman: Allow sections to have an offset
At present sections are always placed automatically. Even if an 'offset'
property is provided it is ignored. Update the logic to support an offset
for sections.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Fri, 26 Apr 2019 03:58:34 +0000 (21:58 -0600)]
binman: Don't show image-skip message by default
This message is not very important since it is simply indicating that the
user's instructions are being followed. Only show it when the verbosity
level is above the default.
Also drop the unnecessary extra newline on this message, which causes two
line breaks.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Simon Glass [Fri, 26 Apr 2019 03:58:33 +0000 (21:58 -0600)]
binman: Don't generate an error in 'text' entry constructor
It is not good practice to raise an exception in a constructor. In this
case the 'text' entry may not actually be used, if -i is used to filter
out the images that get built.
Move the exception to where the data is actually used.
Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Carlo Caione [Thu, 24 Jan 2019 08:54:37 +0000 (08:54 +0000)]
net: phy: realtek: Introduce quirk to mark RXC not stoppable
When EEE is supported by the PHY and the driver allows it, libphy in the
kernel is configuring the PHY to stop receiving the xMII clock while it
is signaling LPI. While this (usually) works fine in the kernel this is
causing issues in U-Boot when rebooting from the linux kernel with this
bit set (without having the possibility to reset the PHY) where the PHY
suddenly stops working.
A new quirk is introduced to unconditionally reset this bit. If the
quirk is not enabled using the proper configuration symbol, the PHY state
is not changed.
Signed-off-by: Carlo Caione <ccaione@baylibre.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Carlo Caione [Fri, 8 Feb 2019 17:25:08 +0000 (17:25 +0000)]
cmd: mdio: Switch to generic helpers when accessing the registers
Switch to use the generic helpers to access the MMD registers so that we
can used the same command also for C45 PHYs, C22 PHYs with direct and
indirect access and PHYs implementing a custom way to access the
registers.
Signed-off-by: Carlo Caione <ccaione@baylibre.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Carlo Caione [Fri, 8 Feb 2019 17:25:07 +0000 (17:25 +0000)]
net: phy: ti: use generic helpers to access MMD registers
Now that generic helpers are available, use those instead of relying on
ti specific functions.
Signed-off-by: Carlo Caione <ccaione@baylibre.com> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Carlo Caione [Fri, 8 Feb 2019 17:25:06 +0000 (17:25 +0000)]
net: phy: Add generic helpers to access MMD PHY registers
Two new helper functions (phy_read_mmd() and phy_write_mmd()) are added
to allow access to the MMD PHY registers.
The MMD PHY registers can be accessed by several means:
1. Using two new MMD access function hooks in the PHY driver. These
functions can be implemented when the PHY driver does not support the
standard IEEE Compatible clause 45 access mechanism described in clause
22 or if the PHY uses its own non-standard access mechanism.
2. Direct access for C45 PHYs and C22 PHYs when accessing the reachable
DEVADs.
3. The standard clause 45 access extensions to the MMD registers through
the indirection registers (clause 22) in all the other cases.
Signed-off-by: Carlo Caione <ccaione@baylibre.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
projects / u-boot.git / log