powerpc: dts: p2020: Do not automatically disable spi@7000 node in p2020-post.dtsi
Device tree include file p2020-post.dtsi should be included after the board
device tree file and overrides settings of the board. So it should not
disable some node as board cannot enable it via normal way (it has to
enable it after inclusion of p2020-post.dtsi file).
Fix it by removal of explicit disable in p2020-post.dtsi file and then
remove explicit post-post enable in all P2020 board device tree files.
Currently no P2020 board has spi@7000 node disabled.
powerpc: dts: p2020: Add Linux compatible string and property for eSDHC
Linux kernel eSDHC driver for P2020 requires additional compatible string
fsl,p2020-esdhc and interrupts property. Add them to p2020-post.dtsi file
to make U-Boot board DTS files compatible for Linux kernel.
powerpc: dts: p2020: Add ptp_clock@24e00 node via pq3-etsec1-timer-0.dtsi
Import pq3-etsec1-timer-0.dtsi device tree include file from upstream Linux
kernel for P2020. This allows U-Boot to use P2020 device tree files from
upstream Linux kernel which reference ptp_clock@24e00 device.
powerpc: dts: p2020: Make PCIe nodes compatible for Linux kernel driver
Linux P2020 PCIe kernel driver uses compatible string fsl,mpc8548-pcie and
needs more DT properties. Copy P2020 PCIe nodes and definitions from
upstream Linux kernel.
powerpc: dts: p2020: Add gpio-controller@fc00 node via pq3-gpio-0.dtsi
Import pq3-gpio-0.dtsi device tree include file from upstream Linux kernel
for P2020. This allows U-Boot to use P2020 device tree files from upstream
Linux kernel which reference gpio-controller@fc00 device.
Do not stringify env $vscfw_addr two times (once implicitly via string
operator "" and second time explicitly via __stringify() macro) and allow
to compile U-Boot without CONFIG_VSC7385_ENET (when __VSCFW_ADDR was not
defined and so macro name was stringified into CONFIG_EXTRA_ENV_SETTINGS).
board: freescale: p1_p2_rdb_pc: Fix page attributes for second 1G SDRAM map
Like for first 1G SDRAM map, do not enable Caching-inhibited nor Guarded
attribute for second 1G SDRAM mapping. Whole 2G SDRAM should use caches and
also allow speculative loading (by not setting Guarded attribute).
Also enable Memory Coherency attribute for second 1G SDRAM map. In commit 316f0d0f8f3c ("powerpc: mpc85xx: Fix static TLB table for SDRAM") it was
enabled for all SDRAM maps on all other boards, just missed this one case.
As a last thing, first 1G SDRAM map has wrong comment, so adjust it.
Currently CONFIG_OF_SEPARATE is completely broken and U-Boot for some
mpc85xx board (e.g. P2020) has to be compiled with CONFIG_OF_EMBED.
Otherwise it crashes during early init.
When debug console is enabled and all debug logging options are turned on
then U-Boot on P2020 with CONFIG_OF_SEPARATE prints following error:
No valid device tree binary found at 110dc300
initcall sequence 110d3560 failed at call 1109535c (err=-1)
### ERROR ### Please RESET the board ###
Problem is with appended DTB. When CONFIG_SYS_MPC85XX_NO_RESETVEC is set
U-Boot binary image without DTB ends immediately after the .u_boot_list
section. At this position is defined _end symbol at which U-Boot expects
start of the appended DTB.
Problem is that after .u_boot_list section are in linker script defined
another sections with 256 byte long padding which are completely empty.
During conversion of U-Boot ELF binary to RAW binary u-boot-nodtb.bin,
objcopy removes trailing zero padding and therefore DTB is appended at
wrong position.
Changing alignment from 256 bytes to 4 bytes fixes this issue. And appended
DTB is finally at he correct position. With this fix U-Boot on P2020 with
CONFIG_OF_SEPARATE option starts working again.
For compatibility with Linux kernel DTS files and also with other U-Boot
powerpc DTS files, rename esdhc@2e000 node to sdhc@2e000 in p1020-post.dtsi
and p2020-post.dtsi include files.
Linux kernel DTS files which include these dtsi files, expect that esdhc
node has name sdhc@2e000 and do not work with other node names.
mmc: fsl_esdhc_spl: pre-PBL: implement redundancy support
QorIQ pre-PBL BootROM scans first 24 SD card sectors (each with fixed 512
bytes length) for boot signature. Implement same redundancy behavior in
fsl_esdhc_spl driver to allow loading proper U-Boot when boot sector is not
the first one.
mtd: rawnand: fsl_elbc: Use ECC configuration from device tree
Initialize ECC configuration after nand_scan_ident() call and only in case
nand_scan_ident() have not done it. nand_scan_ident() fills ECC
configuration from device tree.
Fixes usage of NAND_ECC_SOFT_BCH when it is specified in device tree.
powerpc: dts: p2020: Add serial0 and serial1 via pq3-duart-0.dtsi
Import pq3-duart-0.dtsi device tree include file from upstream Linux kernel
for P2020. This allows U-Boot to use P2020 device tree files from upstream
Linux kernel which reference serial0 or serial1 devices.
powerpc: dts: p2020: Add fsl/p2020si-pre.dtsi and fsl/p2020si-post.dtsi symlinks
P2020 DTS files in upstream Linux kernel use fsl/p2020si-pre.dtsi and
fsl/p2020si-post.dtsi include device tree files.
Add symlinks for these include device tree files into U-Boot powerpc
directory and points them to U-Boot inline device tree files p2020.dtsi and
p2020-post.dtsi.
This allows to use P2020 DTS files from upstream Linux kernel in U-Boot.
board: freescale: p1_p2_rdb_pc: Allow to compile it without env support
When env support is disabled then usage of env_init() or env_relocate()
generates linker errors. So do not compile env_init() or env_relocate()
in SPL code when env support is disabled in SPL.
When env support is disabled then usage of env_get_f() generates linker
errors. So do not compile env_get_f() when env support is disabled (for
example when disabled only in SPL).
When env support is disabled then usage of env_get() generates linker
errors. So do not compile env_get() when env support is disabled (for
example when disabled only in SPL).
mmc: mmc_mode_name() is used also when LOGLEVEL >= LOGL_DEBUG
When CONFIG_LOGLEVEL is set to LOGL_DEBUG or higher then linker throws
error about undefined symbol mmc_mode_name(). So compile mmc_mode_name()
also when CONFIG_LOGLEVEL is set to LOGL_DEBUG or higher.
In pre-PBL header is stored size of code which BootROM copies from SD card
to L2/SRAM. This size has upper limit of L2 cache size. In most cases this
is size of U-Boot SPL or size of L2 cache.
Therefore this size in pre-PBL header cannot be used for determining size
of proper U-Boot.
So always use CONFIG_SYS_MMC_U_BOOT_SIZE for determining size of proper
U-Boot which stored on SD card.
mmc: fsl_esdhc_spl: pre-PBL: check for BOOT signature instead of MBR/DBR
Pre-PBL BootROMs (MPC8536E, MPC8569E, P2020, P1011, P1012, P1013, P1020,
P1021, P1022) require custom BOOT signature on sector 0 and MBR/DBR
signature is not required at all.
So add check for BOOT signature and remove check for MBR/DBR.
This allows U-Boot SPL to load proper U-Boot on pre-PBL BootROMs platforms
also from SD cards which do not have MBR/DBR signature on sector 0.
powerpc: mpc85xx: Rename _start_e500 symbol to _start
The real entry point is _start_e500. There is no _start symbol at all. So
rename _start_e500 to _start for convension that _start symbol is used as
entry point.
_start symbol contains only 32-bit data number 0x27051956 despite it is
marked as text section. This magic number is IH_MAGIC which is used for
marking uboot image header.
mpc85xx start.S code does not define valid uboot image header, so IH_MAGIC
number in _start symbol is useless there.
Moreover this _start symbol is not used at all. Entry point is at symbol
_start_e500.
So because this _start symbol is not used for anything, completely remove
it with IH_MAGIC number. After _start symbol was _start_cont symbol, so
replace all relative address calculations by _start_cont.
Stephen Carlson [Tue, 29 Mar 2022 21:51:10 +0000 (14:51 -0700)]
armv8/fsl-lsch3: Suppress spurious warning on Layerscape CPUs
NXP/Freescale Layerscape CPUs support high-speed serial interfaces (SERDES)
that can be configured for the application. Interfaces not used by the
application can be set to protocol 0 to turn them off and save power, but
U-Boot would emit a warning that 0 was invalid for a SERDES protocol on
boot. Replace the warning text with a notice that the SERDES is disabled.
Signed-off-by: Stephen Carlson <stcarlso@linux.microsoft.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
There is an user-selectable SYS_HAS_ARMV8_SECURE_BASE, which has the
same meaning but is just for the ls1043ardb board. As no in-tree config
uses this, drop it and replace it with something more sophiticated:
ARMV8_PSCI_RELOCATE. This option will then enable the ARMV8_SECURE_BASE
option which is used as the base to relocate the PSCI code (or any code
in the secure region, but that is only PSCI). A SoC (or board) can now
opt-in into having such a secure region by enabling
SYS_HAS_ARMV8_SECURE_BASE. Enable it for the LS1043A SoC, where it was
possible to relocate the PSCI code before as well as on the LS1028A SoC
where there will be PSCI support soon.
Additionally, make ARMV8_PSCI and SEC_FIRMWARE_ARMV8_PSCI exclusive.
Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Michael Walle [Fri, 22 Apr 2022 09:23:27 +0000 (14:53 +0530)]
armv8: layerscape: get rid of smc_call()
There are two different implementations to do a secure monitor call:
smc_call() and arm_smccc_smc(). The former is defined in fwcall.c and
seems to be an ad-hoc implementation. The latter is imported from linux.
smc_call() is also only available if CONFIG_ARMV8_PSCI is not defined.
This makes it impossible to have both PSCI calls and PSCI implementation
in one u-boot build. The layerscape SoC code decide at runtime via
check_psci() if there is a PSCI support. Therefore, this is a
prerequisite patch to add PSCI implementation support for the layerscape
SoCs.
Note, for the TFA part, this is only compile time tested with
(ls1028ardb_tfa_defconfig).
Signed-off-by: Michael Walle <michael@walle.cc>
[Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Michael Walle [Mon, 28 Feb 2022 12:48:37 +0000 (13:48 +0100)]
armv8: include psci_update_dt() unconditionally
psci_update_dt() is also required if CONFIG_ARMV8_PSCI is set, that is,
if u-boot is the PSCI provider.
Guard the check which is intended to call into the PSCI implementation
in the secure firmware, by the proper macro SEC_FIRMWARE_ARMV8_PSCI.
Mark the function as weak because - unfortunately - there is already
a stub of the same function in arch/arm/mach-rmobile/psci-r8a779a0.c
which does not the same as the common one.
Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
Sean Anderson [Fri, 22 Apr 2022 08:31:36 +0000 (14:01 +0530)]
arm: layerscape: Disable erratum A009007 on LS1021A, LS1043A, and LS1046A
This erratum is reported to cause problems on these processors [1-3].
The problem is usually with the clocking, which is supposed to be
configured by the RCW [4]. However, if it is not set, or if the default
clocking is not correct, then this erratum will cause an SError.
However, according to Ran Wang in [1]:
" ... this erratum is used to pass USB compliance test only, you could
disable this workaround on your board if you don't any USB issue on
normal use case, I think it's fine."
So just disable this erratum by default for these processors.
Signed-off-by: Sean Anderson <sean.anderson@seco.com> Acked-by: Ran Wang <ran.wang_1@nxp.com>
[Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
Tom Rini [Sat, 23 Apr 2022 12:06:28 +0000 (08:06 -0400)]
Merge branch '2022-04-22-assorted-updates'
- Add "-q" to fdt addr and use it in distro_bootcmd to make the user
experience less scary reading in normal try/fail cases.
- Let the adc update an environment variable like many other commands do
- Fix TPL SEPARATE_BSS check when locating DTB
- Allow ":" in PXE file names again
- Two Apple M1 fixes
Mark Kettenis [Tue, 19 Apr 2022 19:20:31 +0000 (21:20 +0200)]
arm: apple: Point stdout-path to framebuffer when keyboard present
Unless you have a spare Apple Silicon machine, getting access to
the serial port on Apple Silicon machines requires special
hardware. Given that most machines come with a built-in screen
the framebuffer is likely to be the most convenient output device
for most users. While U-Boot will output to both serial and
framebuffer, OSes might not. Therefore set stdout-path to point
at /chosen/framebuffer when a keyboard is connected to the machine.
This behaviour can be overridden by setting the "stdout" variable
in the U-Boot environment. I addition to that keep the serial
console as the default when running under the m1n1 hypervisor.
The m1n1 hypervisor virtualizes the serial port such that it
can be easily accessed from any other machine with a USB port.
Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Reviewed-by: Janne Grunau <j@jannau.net> Tested-by: Janne Grunau <j@jannau.net>
Mark Kettenis [Tue, 19 Apr 2022 19:10:29 +0000 (21:10 +0200)]
arm: apple: Don't clear framebuffer
Enable CONFIG_NO_FB_CLEAR to preserve the Asahi logo. Since that
logo is drawn on a black background also enable
CONFIG_SYS_WHITE_ON_BLACK such that text printed by U-Boot is still
visible.
Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Lyle Franklin [Sat, 16 Apr 2022 15:36:43 +0000 (11:36 -0400)]
Allow colon in PXE bootfile URLs
- U-boot's PXE flow supports prefixing your bootfile name with an
IP address to fetch from a server other than the DHCP server,
e.g. `hostIPaddr:bootfilename`:
https://github.com/u-boot/u-boot/commit/a93907c43f847f076dd0e34ee3b69b5e8e6d0d29
- However, this breaks bootfile paths which contain a colon, e.g.
`f0:ad:4e:10:1b:87/7/pxelinux.cfg/default`
- This patch checks whether the `hostIPaddr` prefix is a valid
IP address before overriding the serverIP otherwise the whole
bootfile path is preserved
Signed-off-by: Lyle Franklin <lylejfranklin@gmail.com>
The documentation for CONFIG_IS_ENABLED() in include/linux/kconfig.h
implies that we will get the correct behaviour, but the actual behaviour
differs such that this condition is now always false.
This stopped TPL being able to load the device tree blob at least on the
ROCKPro64 board (RK3399 SoC), since the wrong device tree location was
chosen.
The issues causing this behaviour with CONFIG_IS_ENABLED() are:
1. The documentation implies that CONFIG_SPL_BUILD =>
CONFIG_SPL_<option> is considered before the TPL equivalent.
Actually, the TPL options have higher priority - see definition of
_CONFIG_PREFIX.
2. The documentation implies a fallthrough, eg. if CONFIG_SPL_BUILD is
defined but the CONFIG_SPL_<option> is not, then it will proceed to
check if CONFIG_TPL_BUILD
Actually, if CONFIG_TPL_BUILD is defined, then it stops there
and CONFIG_SPL_BUILD is not considered - see definition of
_CONFIG_PREFIX.
During TPL build, at least for the ROCKPro64, both CONFIG_TPL_BUILD
and CONFIG_SPL_BUILD are defined, but because of the above, only TPL
options are considered. Since there is no CONFIG_TPL_SEPARATE_BSS,
this fails.
Fixes: 690af71850 ("fdt: Correct condition for SEPARATE_BSS") Signed-off-by: Andrew Abbott <andrew@mirx.dev>
Sean Anderson [Wed, 23 Mar 2022 18:26:09 +0000 (14:26 -0400)]
power-domain: Fix use of uninitialized value in dev_power_domain_ctrl
If dev_count_phandle_with_args returns 0 or another error, then pd will never
have been initialized by power_domain_get_by_index. Avoid comparing against
pd.dev in this situation.
Fixes: 3e4fcfa4bc ("power-domain: fix hang in endless loop on i.MX8") Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
Michal Simek [Wed, 9 Mar 2022 09:05:45 +0000 (10:05 +0100)]
usb: dwc3: Add support for usb3-phy PHY configuration
When usb3-phy label is found, PHY driver is called and serdes line is
initialized. This is preparation for serdes/psgtr driver to configure GT
lines based on description in DT.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Jim Liu [Fri, 1 Apr 2022 09:59:39 +0000 (17:59 +0800)]
wdt: nuvoton: Add support for Nuvoton
Add watchdog controller driver for NPCM7xx/npcm8xx
the wdt design of npcm750 and npcm845 is the same.
so the driver can work on npcm750 and npcm845.
about npcm845 wdt dtsi i will followed kernel dts name
to use nuvoton,npcm750-wdt.
Signed-off-by: Jim Liu <JJLIU0@nuvoton.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini [Thu, 21 Apr 2022 23:55:38 +0000 (19:55 -0400)]
Merge branch '2022-04-21-further-cleanups'
- Fix SPL_SYS_MALLOC_SIMPLE and non-SPL_FRAMEWORK boards (a large number
of PowerPC platforms)
- Remove duplication of crc16 functionality
- Migrate COUNTER_FREQUENCY to CONFIG_COUNTER_FREQUENCY and have it in
Kconfig
Currently the space between kernel_addr_r and the fdt_addr_r is only 32MB.
To have enough space to load kernel images bigger than 32MB change the
variables to a feasible value.
The new environment variables layout is based on the scheme from
"include/configs/ti_armv7_common.h".
The CONFIG_SYS_LOAD_ADDR value is set to 0x42000000. With that we have
the same value as for the kernel_addr_r.
Signed-off-by: Heiko Thiery <heiko.thiery@gmail.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
In arch/arm/mach-imx/imx8m/soc.c there's an implementation of
board_fix_fdt() introduced by commit 35bb60787b88. Remove the
redundant one to avoid failed to build from source when enabling
CONFIG_OF_BOARD_FIXUP.
Peng Fan [Wed, 13 Apr 2022 09:47:19 +0000 (17:47 +0800)]
arch: arm: Kconfig: set default COUNTER_FREQUENCY
Set default COUNTER_FREQUENCY according to config header file
under include/configs/
i.MX6UL/ULL/7D/8QM/8QXP all has system counter frequency run at 8MHz,
so set default value for them.
SUNXI/EXYNOS/ROCKCHIP_RK3128/ROCKCHIP_RK3288/ROCKCHIP_RK322X/ROCKCHIP_RK3036
at 24MHz. ARCH_LX2160A at 25MHz
ARCH_ZYNQMP at 100MHz
fs: ext4: Use CRC-16 implementation from linux/crc16.h
Implementation in linux/crc16.h provides standard CRC-16 algorithm with
polynomial x^16 + x^15 + x^2 + 1. Use it and remove duplicate ext4 CRC-16
specific code.
Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
crc16-ccitt: Rename file with CRC-16-CCITT implementation to crc16-ccitt.c
U-Boot CRC-16 implementation uses polynomial x^16 + x^12 + x^5 + 1 which is
not standard CRC-16 algorithm, but it is known as CRC-16-CCITT. Rename file
crc16.c to crc16-ccitt.c to reduce confusion.
Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
Inspection showed that gd->malloc_limit is zero. And it is because
generally SPL_FRAMEWORK initialize SPL's gd->malloc_limit. But when
SPL_FRAMEWORK is not enabled then in most cases nobody initialize
gd->malloc_limit and so SPL malloc simple does not work.
So disable SPL_SYS_MALLOC_SIMPLE by default when SPL_FRAMEWORK is not
enabled. SPL_SYS_MALLOC_SIMPLE can be disabled only by setting
SPL_SYS_MALLOC_F_LEN to zero. So do it.
This change fixes SPL error "alloc space exhausted" on P2020 board.
Tom Rini [Thu, 21 Apr 2022 14:56:58 +0000 (10:56 -0400)]
Merge branch '2022-04-21-assorted-improvements'
- For the environment, add a arch_env_get_location hook and make use of
it on some NXP platforms (so that boards can override SoCs).
- Remove some unused squashfs code from SPL
- Resync am335x beaglebone related DTS files
- Enable SPL_SEPARATE_BSS if SPL_BSS_START_ADDR is used
Enable DM_SERIAL for both U_Boot and the SPL. The uart4 and its pinmux
are already marked with u-boot,dm-spl but we need to move the call to
preloader_console_init() after spl_init() to avoid a board hang
as dm can't be used until after spl_init().
Remove the manual config of the UART pinmux now that it is no longer
needed.
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com> Cc: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Fabio Estevam <festevam@denx.de> Tested-by: Ariel D'Alessandro <ariel.dalessandro@collabora.com>
projects / u-boot.git / log