Marek Vasut [Fri, 13 Apr 2018 22:01:19 +0000 (00:01 +0200)]
ARM: rmobile: Zap CONFIG_MMC_RENESAS_TUNING
Drop the CONFIG_MMC_RENESAS_TUNING symbol from Gen3 configs.
This symbol is no longer used after the Matsushita SDHI driver,
instead the renesas-sdhi driver uses CONFIG_MMC_HS200_SUPPORT
to discern whether the tuning support should be compiled in.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Tom Rini <trini@konsulko.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
--
V2: Submit this on top of configs which are actually in mainline
Marek Vasut [Fri, 13 Apr 2018 21:13:00 +0000 (23:13 +0200)]
ARM: rmobile: Convert TPL to SPL
There is currently no use for building the SPL anymore, since the
SPI loader can easily be replaced by TPL and TPL does load U-Boot
directly. Upgrade TPL to SPL and replace what used to be SPL with
it. This way we build the U-Boot sources only twice, not thrice.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Marek Vasut [Fri, 13 Apr 2018 13:51:13 +0000 (15:51 +0200)]
ARM: rmobile: Shrink the TPL
Shrink the TPL by using tiny printf and tiny memset by default.
This removes the biggest symbol -- vsnprintf_internal -- from
the TPL and reduces the text segment by about 2 kiB.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Marek Vasut [Thu, 12 Apr 2018 13:23:46 +0000 (15:23 +0200)]
ARM: rmobile: Update H2 Stout
The H2 Stout port was broken since some time. This patch updates
the H2 Stout port to use modern frameworks, DM, DT probing, SPL
and TPL for the preloading and puts it on par with the M2 Porter
board.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Tom Rini [Tue, 10 Apr 2018 15:51:53 +0000 (11:51 -0400)]
configs: Fixup some CPSW-related items
- For am335x_pdu001 we do not want the CPSW driver, drop it
- Re-sync the defconfig for am43xx_evm_rtconly as it came in after the
patch that converted CPSW to Kconfig was posted but before it was
applied.
- Drop empty section / comments from pengwyn
- Drop empty section / comments from baltos and drop unused
CONFIG_SPL_NET_VCI_STRING (it does not enable CONFIG_SPL_NET_SUPPORT
currently and SPL_NET_VCI_STRING has been migrated already).
Cc: Felix Brack <fb@ltec.ch> Cc: Lokesh Vutla <lokeshvutla@ti.com> Cc: Yegor Yefremov <yegorslists@googlemail.com> Cc: Lothar Felten <lothar.felten@gmail.com> Fixes: f02b8d17619f ("Migrate CONFIG_DRIVER_TI_CPSW to Kconfig") Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Felix Brack <fb@ltec.ch> Tested-by: Felix Brack <fb@ltec.ch>
Marek Vasut [Thu, 15 Feb 2018 12:19:33 +0000 (13:19 +0100)]
ARM: rmobile: Fix the memory map on Gen3
Fix up the memory map on Gen3 to match datasheet properly.
This simplifies the memory map setup as well, since we do
no longer need this massive complexity.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Marek Vasut [Tue, 10 Apr 2018 14:43:47 +0000 (16:43 +0200)]
spi: sh_qspi: Make use of the 32byte FIFO
The QSPI controller on RCar Gen2 has 32byte FIFO. Instead of doing
the SPI transmission 1 byte at time, if there is a 32byte chunk of
data to be transferred, fill the FIFO completely and then transfer
the data to/from the FIFO. This increases the SPI NOR access speed
significantly.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Marek Vasut [Tue, 10 Apr 2018 14:58:46 +0000 (16:58 +0200)]
spi: sh_qspi: Replace ad hoc waiting with wait_for_bit
Replace the ad-hoc endless loops with wait_for_bit() with
reasonable timeout. Note that the loops had internal 10uS
delays, although there is no reason for those on this HW,
so they are dropped.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
Marek Vasut [Wed, 29 Nov 2017 05:29:46 +0000 (06:29 +0100)]
mtd: spi: Add Renesas RPC SPI-flash driver
Add driver for the RPC block in SPI-flash mode. This driver allows
access to a SPI NOR flash attached to the RPC block and does not
support RPC in Hyperflash mode. Note that this block is extremely
selective when communicating with the SPI NOR.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Marek Vasut [Sat, 19 Aug 2017 21:24:08 +0000 (23:24 +0200)]
mtd: rpc: Add Renesas RPC Hyperflash driver
Add driver for the RPC block in Hyperflash mode. This driver allows
access to a CFI Hyperflash attached to the RPC block and does not
support RPC in SPI mode.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Marek Vasut [Mon, 9 Apr 2018 18:47:31 +0000 (20:47 +0200)]
mmc: matsushita-common: Wait for command completion
Make sure to wait for the command to complete altogether, including
the trailing 8 clock cycles. This prevents the driver for accidentally
writing the CMD register too fast before the previous command fully
completed.
Marek Vasut [Mon, 9 Apr 2018 18:47:31 +0000 (20:47 +0200)]
mmc: matsushita-common: Special case only select registers in 16bit
There are only a few registerse used in the 16bit mode which are
32bit internally. Special-case only those in the IO accessors and
always write both halves. Any other register access is protected
from accidentally overwriting neighboring register.
Marek Vasut [Sat, 23 Sep 2017 11:01:20 +0000 (13:01 +0200)]
mmc: matsushita-common: Always check controller version
Handle the controller version even if quirks are set. The controller in
Renesas Gen3 SoCs does provide the version register, which indicates a
controller v10 and the controller does support internal DMA and /1024
divider.
Marek Vasut [Tue, 2 Jan 2018 18:40:49 +0000 (19:40 +0100)]
mmc: matsushita-common: Handle DMA completion flag differences
The DMA READ completion flag position differs on Socionext and Renesas
SoCs. It is bit 20 on Socionext SoCs and using bit 17 is a hardware bug
and forbidden. It is bit 17 on Renesas SoCs and bit 20 does not work on
them.
Marek Vasut [Tue, 26 Sep 2017 18:34:35 +0000 (20:34 +0200)]
mmc: matsushita-common: Handle Renesas div-by-1
On the Renesas version of the IP, the /1 divider is realized by
setting the clock register [7:0] to 0xff instead of setting bit
10 of the register. Check the quirk and handle accordingly.
Marek Vasut [Sun, 8 Apr 2018 16:49:52 +0000 (18:49 +0200)]
mmc: matsushita-common: Add Renesas RCar quirks
Add a quirk to identify that the controller is Renesas RCar variant
of the Matsushita SD IP and another quirk indicating it can support
Renesas RCar HS200/HS400/SDR104 modes.
Marek Vasut [Sun, 8 Apr 2018 16:14:22 +0000 (18:14 +0200)]
mmc: renesas-sdhi: Handle 16bit IP
The Renesas RCar Gen2 chips have a mix of 32bit and 16bit variants
of the IP. There is no DT property which allows discerning those,
so what Linux does is it checks the size of the register area and
if it is 0x100, the IP is 16bit, otherwise the IP is 32bit. Handle
the distinction the same way.
Marek Vasut [Sun, 8 Apr 2018 15:45:23 +0000 (17:45 +0200)]
mmc: uniphier: Allow passing quirks to the probe function
Certain instances of the SD IP require more elaborate digging
in the DT to figure out which variant of the SD IP is in use.
Allow explicit passing of the quirks into the probe function.
Marek Vasut [Sun, 8 Apr 2018 15:41:14 +0000 (17:41 +0200)]
mmc: uniphier: Add support for 16bit variant
Add support for 16bit mutation of the Matsushita SD IP. Since some
registers are internally 32bit, the matsu_sd_{read,write}l() has
to special-case this 16bit variant a bit.
Marek Vasut [Sun, 8 Apr 2018 15:25:49 +0000 (17:25 +0200)]
mmc: uniphier: Drop useless check
Drop useless check in matsu_sd_{read,write}q(), this is only ever
called to read the data from FIFO and only when 64bit variant of
the block is used anyway.
Marek Vasut [Sun, 8 Apr 2018 15:14:42 +0000 (17:14 +0200)]
mmc: uniphier: Factor out FIFO accessors
Add macros to generate the FIFO accessors, since the code is almost
the same with only minor differences. This is done in preparation
for adding 16bit variant of the IP.
Marek Vasut [Sun, 8 Apr 2018 13:22:58 +0000 (15:22 +0200)]
mmc: uniphier: Split out SoC specific bits from the driver
Factor out common code from the uniphier SD driver, change the prefix
of the functions from uniphier_sd_ to matsu_sd_ and create separate
renesas-sdhi.c driver. Thus far, all the code is still compiled when
CONFIG_UNIPHIER_MMC is selected and there is no functional change.
This patch is a preparation for further split of the SoC specific
parts of the Matsushita SD driver, used both on Uniphier and R-Car.
Marek Vasut [Sat, 7 Apr 2018 14:16:30 +0000 (16:16 +0200)]
ARM: rmobile: Add JTAG recovery support for M2 Porter
Add JTAG recovery support into the M2 Porter TPL. This allows the
TPL to be loaded over JTAG, initialize the system, wait for the
JTAG debugger to load U-Boot image into RAM and then resume and
start U-Boot from RAM.
The procedure is as follows:
1) Load u-boot-tpl.bin to 0xe6300000
2) Write magic number 0x1337c0de to 0xe6300020
TPL checks for this particular magic and starts JTAG recovery
if this number is present. This is not present by default.
3) Start U-Boot TPL from 0xe6300000
4) Wait for a message from TPL on UART indicating JTAG boot:
"JTAG boot detected!"
5) Halt the system in JTAG debugger
6) Load U-Boot image (u-boot.img) to 0x4fffffc0
7) Write magic number 0xb33fc0de to 0xe6300024
TPL checks for this particular magic to verify that the U-Boot
image was loaded into DRAM by the JTAG debugger.
8) Resume the system in JTAG debugger
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Marek Vasut [Tue, 3 Apr 2018 10:52:48 +0000 (12:52 +0200)]
ARM: rmobile: Add TPL support on R8A7791 M2 Porter
Add and enable TPL on M2 Porter. The TPL must fit into 16 kiB due
to the Gen2 BootROM restriction. The TPL is running from MERAM and
is capable of performing the initial initialization of PFC, Clock,
GPIO, LBSC, DBSC and QSPI NOR. DBSC is responsible for bringing up
the DDR DRAM access. The TPL is capable of loading the next stage,
U-Boot, from either SPI NOR or UART as a fallback. If either does
provide a valid U-Boot uImage, the system stops, which allows the
operator to load U-Boot ie. via JTAG and start it manually.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Marek Vasut [Sat, 7 Apr 2018 15:03:28 +0000 (17:03 +0200)]
spl: ram: Convert to CONFIG_IS_ENABLED
This patch is a preparation for adding TPL support for RAM loading.
CONFIG_IS_ENABLED allows for proper handling of the U-Boot/SPL/TPL
differences in config symbol names.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Tom Rini <trini@konsulko.com>
Marek Vasut [Sat, 7 Apr 2018 14:06:36 +0000 (16:06 +0200)]
ARM: Fix Makefile during SPL and TPL build
The tiny variants of memset and memcpy implementations can be
built for TPL as well, check whether a TPL build is in progress
and avoid including the default variants.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com>
Marek Vasut [Sat, 7 Apr 2018 14:06:22 +0000 (16:06 +0200)]
serial: Fix Makefile during SPL and TPL build
This patch fixes a situation where CONFIG_DM_SERIAL is enabled for
regular U-Boot and SPL, but not for TPL. In that case, the build
will try to include serial-uclass into the TPL nonetheless, because
CONFIG_DM_SERIAL is set.
The solution is to check if the build is for SPL or TPL and in that
case, check if CONFIG_$(SPL_TPL_)DM_SERIAL is also set. Only in that
case, include serial-uclass.c . If the build is for regular U-Boot,
CONFIG_BUILD is not set, so only check if CONFIG_DM_SERIAL is set
and if so, include serial-uclass.c
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com>
The Amlogic Meson GXL and GXM (simple variant) embeds up to 3 USB2 PHYs
and an USB3 PHY. This patch adds drivers for these for the standard generic
PHY interface and supports the power-on/off calls and set the Host mode by
default.
They are based on the excellent work from Martin Blumenstingl merged in linux.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Neil Armstrong [Wed, 11 Apr 2018 15:08:01 +0000 (17:08 +0200)]
usb: host: dwc3: Add support for multiple PHYs
DWC3 Ips can have more than 1 PHY for USB2 and 1 PHY for USB3, add support
for a generic number of PHYs and adapt the code to handle a generic
number of PHYs.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
The commit implement a gpio-based software deblocking. The code
extract I2C pins description from device tree, switch pins to GPIO
mode, toggle SCL until slave release SDA, send I2C stop and switch
I2C pins back to I2C mode.
Signed-off-by: Alexander Kochetkov <al.kochet@gmail.com>
The mutex lock and unlock functions are stubbed out and mutex_is_locked
was 0. This caused asserts to fail in ubifs code when checking that the
mutex was locked. For example,
UBIFS assert failed in ubifs_change_lp at 540
UBIFS assert failed in ubifs_release_lprops at 278
Assume that the "mutex" is locked since that is the normal case when it
is checked in the ubifs code.
Neil Armstrong [Tue, 3 Apr 2018 09:40:51 +0000 (11:40 +0200)]
reset: add sandbox test for bulk API
This patch adds the bulk reset API tests for the sandbox test suite.
Unlike the main test, it also check the "other" reset signal using the bulk API
and checks if the resets are correctly asserted/deasserted.
To allow the bulk API to work, and avoid changing the DT, the number of resets
of the sandbox reset controller has been bumped to 101 for the "other" reset
line to be valid.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Guillaume GARDET [Fri, 30 Mar 2018 08:28:19 +0000 (10:28 +0200)]
mkimage: do not fail if there is no print_header function
Commit 253c60a breaks the exit value of 'mkimage -T rkimage'
and print the following error:
mkimage: Can't print header for Rockchip Boot Image support: Success
It is not a failure to not print headers, so just display the warning message,
and finish the function properly.
Signed-off-by: Guillaume GARDET <guillaume.gardet@free.fr> Cc: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Neil Armstrong [Thu, 29 Mar 2018 12:56:02 +0000 (14:56 +0200)]
serial: meson: Update compatible with new Linux bindings
The Amlogic Meson SoCs serial bindings were not written when serial
support was pushed into Linux and U-Boot.
A clean bindings document has been merged into Linux tree to correctly
handle the multiple clocks feeding the serial peripheral.
This update the U-Boot serial_meson driver with the new compatible
string for Amlogic Meson GX Socs.
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini [Mon, 9 Apr 2018 15:05:44 +0000 (11:05 -0400)]
Merge tag 'signed-efi-next' of git://github.com/agraf/u-boot
Patch queue for efi - 2018-04-09
Highlights this time around:
- Lots of minor spec compliance fixes
- Support full range of GOP BLT commands
- More fine grained error checking
- Network fixes (init, DP)
- Lots of other bug fixes...
projects / u-boot.git / log