Lokesh Vutla [Fri, 8 Mar 2019 06:17:32 +0000 (11:47 +0530)]
firmware: Add support for querying msmc memory
DMSC can use certain amount of msmc memory available in the
system. Also certain part of msmc memory can be marked as L3
cache using board config. But users might not know what size
is being used and the remaining available msmc memory. In order
to fix this TISCI protocol provides a messages that can query
the available msmc memory in the system. Add support for this
message.
board: ti: dra71: Add pinmux settings for NAND on DRA71x EVM
By default VOUT3 occupies the pins required for NAND. Therefore, create
a seperate entry that can be use to reconfigure these pins to work for
NAND.
On the EVM SWITCH 8 pins 0 and 1 will be used to determine if NAND is
enabled or not. For NAND to be selected pin 0 should be on and pin 1
should be off. Any other combination will assume NAND shouldn't be
enabled.
Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com> Signed-off-by: Faiz Abbas <faiz_abbas@ti.com>
Adam Ford [Tue, 26 Feb 2019 03:53:47 +0000 (21:53 -0600)]
ARM: davinci: da850evm: Enable SPL_OF_CONTROL without PLATDATA
With the memory mapping giving us some more avialable RAM, this
updates the da850-evm-u-boot.dtsi to include the serial port, SPI
and Flash nodes along with some dependent nodes in the SPL dtb.
This also removes the platform data initialization code for the
serial port and SPI Flash.
Adam Ford [Tue, 26 Feb 2019 03:53:46 +0000 (21:53 -0600)]
davinci: da850evm/omapl138-lcdk: Move BSS to SDRAM because SRAM is full
In order to fully support SPL_OF_CONTROL, we need BSS to be a bit
larger. This patch relocates BSS to SDRAM instead of SRAM which
is similar to how ARMv7 boards (like OMAP2+) do it.
This means two new variables are required:
CONFIG_SPL_BSS_START_ADDR set to DAVINCI_DDR_EMIF_DATA_BASE
CONFIG_SPL_BSS_MAX_SIZE is set to 0x1080000 which is 1 byte
before the location where U-Boot will load.
Martyn Welch [Mon, 25 Feb 2019 15:32:59 +0000 (15:32 +0000)]
env: Don't check CONFIG_ENV_OFFSET_REDUND for SPL build
When booting using an SPL on am335x, if we want to support booting with
the boot ROM loader via USB (which uses RNDIS, making bootp and tftp
calls) we need to enable gadget eth in the SPL to load the main U-Boot
image. To enable CONFIG_SPL_ETH_SUPPORT, we must enable
CONFIG_SPL_ENV_SUPPORT as the environment is used by the eth support, but
we don't actually need to have environment variables saved in the SPL
environment. We do however have environment variables saved in the main
U-Boot image and enable CONFIG_ENV_OFFSET_REDUND (we are storing in raw
NAND). In such instances, even with the build config enabling both
CONFIG_CMD_SAVEENV and CONFIG_CMD_NAND, these options aren't set when
building the SPL, but CONFIG_ENV_OFFSET_REDUND still is.
Don't check this configuration option for SPL builds to enable the above
configuration.
Signed-off-by: Martyn Welch <martyn.welch@collabora.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Murali Karicheri [Thu, 21 Feb 2019 17:02:07 +0000 (12:02 -0500)]
ARM: dts: k2g-ice: add dt node for netcp
This patch adds dt node for DP83867 phy used on K2G ICE board and
also enable netcp device nodes for the board.
EVM hardware spec recommends to add 0.25 nsec delay in the tx
direction and 2.25 nsec delay in the rx direction for internal
delay in the clock path to be on the safer side.
The board straps RX_DV/RX_CTRL pin of on board DP83867 phy in mode
1. Unfortunately, the phy data manual disallows this. Add
ti,dp83867-rxctrl-strap-quirk in the phy node to allow software to
enable workaround suggested for this incorrect strap setting. This
ensures proper operation of this PHY.
The dts bindings are kept in sync with that from 4.14.y linux
kernel. This required the pinmux device related bindings to be
commented out to allow for compilation.
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Murali Karicheri [Thu, 21 Feb 2019 17:02:05 +0000 (12:02 -0500)]
ARM: dts: k2g-evm: remove unused phy-mode property from phy node
This patch removes the unused phy-mode property from the phy dt node. On
K2G, currently link-interface determines if phy is used or not and is
already set to use rgmii. So this is not needed. Besides phy-mode should
be added to slave interface configuration of the cpsw driver, not in the
phy node.
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Murali Karicheri [Thu, 21 Feb 2019 17:02:04 +0000 (12:02 -0500)]
ARM: k2g: add a workaround to reset the phy
This patch adds a workaround to reset the phy one time during boot
using GPIO0 pin 10 to make sure, the Phy latches the configuration
from the input pins correctly.
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Murali Karicheri [Thu, 21 Feb 2019 17:02:01 +0000 (12:02 -0500)]
ARM: k2g-ice: Add pinmux support for rgmii interface
This add pinmux configuration for rgmii interface so that network
driver can be supported on K2G ICE boards. The pinmux configurations
for this are generated using the pinmux tool at
https://dev.ti.com/pinmux/app.html#/default
As this required some BUFFER_CLASS definitions, same is re-used
from the linux defnitions in include/dt-bindings/pinctrl/keystone.h
Vignesh R [Tue, 5 Feb 2019 12:01:24 +0000 (17:31 +0530)]
dma: ti: add driver to K3 UDMA
The UDMA-P is intended to perform similar (but significantly upgraded) functions
as the packet-oriented DMA used on previous SoC devices. The UDMA-P module
supports the transmission and reception of various packet types.
The UDMA-P also supports acting as both a UTC and UDMA-C for its internal
channels. Channels in the UDMA-P can be configured to be either Packet-Based or
Third-Party channels on a channel by channel basis.
The Ring Accelerator (RINGACC or RA) provides hardware acceleration to
enable straightforward passing of work between a producer and a consumer.
There is one RINGACC module per NAVSS on TI AM65x SoCs.
The RINGACC converts constant-address read and write accesses to equivalent
read or write accesses to a circular data structure in memory. The RINGACC
eliminates the need for each DMA controller which needs to access ring
elements from having to know the current state of the ring (base address,
current offset). The DMA controller performs a read or write access to a
specific address range (which maps to the source interface on the RINGACC)
and the RINGACC replaces the address for the transaction with a new address
which corresponds to the head or tail element of the ring (head for reads,
tail for writes). Since the RINGACC maintains the state, multiple DMA
controllers or channels are allowed to coherently share the same rings as
applicable. The RINGACC is able to place data which is destined towards
software into cached memory directly.
Supported ring modes:
- Ring Mode
- Messaging Mode
- Credentials Mode
- Queue Manager Mode
TI-SCI integration:
Texas Instrument's System Control Interface (TI-SCI) Message Protocol now
has control over Ringacc module resources management (RM) and Rings
configuration.
The Ringacc driver manages Rings allocation by itself now and requests
TI-SCI firmware to allocate and configure specific Rings only. It's done
this way because, Linux driver implements two stage Rings allocation and
configuration (allocate ring and configure ring) while TI-SCI Message
Protocol supports only one combined operation (allocate+configure).
Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Vignesh R <vigneshr@ti.com>
firmware: ti_sci: Add support for NAVSS resource management
Texas Instruments' System Control Interface (TI-SCI) Message Protocol
abstracts management of NAVSS resources, like PSI-L pairing and
unpairing, UDMAP tx/rx/flow configuration and Rings.
This patch adds support for requesting and configuring such resources
from TI-SCI firmware.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com> Signed-off-by: Grygorii Strashko <grygorii.strashko@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Vignesh R <vigneshr@ti.com>
Tom Rini [Tue, 9 Apr 2019 20:08:52 +0000 (16:08 -0400)]
test.py: Disable fsck for FAT tests for now
Currently enabling fsck on FAT16/FAT32 exposes that we have problems
with:
TestFsBasic.test_fs13[fat16]
TestFsBasic.test_fs11[fat32]
TestFsBasic.test_fs12[fat32]
TestFsBasic.test_fs13[fat32]
TestFsExt.test_fs_ext1[fat32]
TestFsExt.test_fs_ext2[fat32]
TestFsExt.test_fs_ext3[fat32]
TestFsExt.test_fs_ext4[fat32]
TestFsExt.test_fs_ext5[fat32]
TestFsExt.test_fs_ext6[fat32]
TestFsExt.test_fs_ext7[fat32]
TestFsExt.test_fs_ext8[fat32]
TestFsExt.test_fs_ext9[fat32]
TestMkdir.test_mkdir6[fat16]
TestMkdir.test_mkdir1[fat32]
TestMkdir.test_mkdir2[fat32]
TestMkdir.test_mkdir3[fat32]
TestMkdir.test_mkdir4[fat32]
TestMkdir.test_mkdir5[fat32]
TestMkdir.test_mkdir6[fat32]
TestUnlink.test_unlink1[fat16]
TestUnlink.test_unlink2[fat16]
TestUnlink.test_unlink3[fat16]
TestUnlink.test_unlink4[fat16]
TestUnlink.test_unlink5[fat16]
TestUnlink.test_unlink6[fat16]
TestUnlink.test_unlink7[fat16]
TestUnlink.test_unlink1[fat32]
TestUnlink.test_unlink2[fat32]
TestUnlink.test_unlink3[fat32]
TestUnlink.test_unlink4[fat32]
TestUnlink.test_unlink5[fat32]
TestUnlink.test_unlink6[fat32]
TestUnlink.test_unlink7[fat32]
This is because we don't update the "information sector" on FAT32.
While in the future we should resolve this problem and include that
feature, we should enable fsck for ext4 to ensure that things remain in
good shape there.
Benjamin Lim [Fri, 29 Mar 2019 11:29:45 +0000 (07:29 -0400)]
Fix ext4 block group descriptor sizing
Ext4 allows for arbitrarily sized block group descriptors when 64-bit
addressing is enabled, which was previously not properly supported. This
patch dynamically allocates a chunk of memory of the correct size.
Marek Vasut [Wed, 13 Mar 2019 16:49:29 +0000 (17:49 +0100)]
test/py: mmc: Add 'mmc read' performance check
Add option to the mmc rd test to check the duration of the
execution of the mmc read command. This allows intercepting
read performance regressions.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
Marek Vasut [Wed, 13 Mar 2019 16:49:28 +0000 (17:49 +0100)]
test/py: mmc: Add 'mmc info' test
Add test for 'mmc info' subcommand. This tests whether the card
information is obtained correctly and verifies the device, bus
speed, bus mode and bus width.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
Marek Vasut [Wed, 13 Mar 2019 16:49:27 +0000 (17:49 +0100)]
test/py: mmc: Add 'mmc rescan' test
Add test for 'mmc rescan' subcommand. This tests whether the
system can switch to a specific card and then rescan the card.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
Marek Vasut [Wed, 13 Mar 2019 16:49:26 +0000 (17:49 +0100)]
test/py: mmc: Add 'mmc dev' test
Add separate test for 'mmc dev' subcommand. This tests whether
the system can switch to a specific card.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
Marek Vasut [Wed, 13 Mar 2019 16:49:25 +0000 (17:49 +0100)]
test/py: mmc: Factor out device selection
Factor out the 'mmc dev' call so it can be recycled by other tests.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Tom Rini <trini@konsulko.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
A FAT12/FAT16 root directory location is specified by a sector offset and
it might not start at a cluster boundary. It also resides before the
data area (before cluster 2).
However, the current code assumes that the root directory is located at
a beginning of a cluster, causing no files to be found if that is not
the case.
Since the FAT12/FAT16 root directory is located before the data area
and is not aligned to clusters, using unsigned cluster numbers to refer
to the root directory does not work well (the "cluster number" may be
negative, and even allowing it be signed would not make it properly
aligned).
Modify the code to not use the normal cluster numbering when referring to
the root directory of FAT12/FAT16 and instead use a cluster-sized
offsets counted from the root directory start sector.
This is a relatively common case as at least the filesystem formatter on
Win7 seems to create such filesystems by default on 2GB USB sticks when
"FAT" is selected (cluster size 64 sectors, rootdir size 32 sectors,
rootdir starts at half a cluster before cluster 2).
dosfstools mkfs.vfat does not seem to create affected filesystems.
Signed-off-by: Anssi Hannula <anssi.hannula@bitwise.fi> Reviewed-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com> Tested-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com>
Gero Schumacher [Tue, 26 Feb 2019 15:45:22 +0000 (15:45 +0000)]
fs: ext4: Problem with ext4load and sparse files
Hi,
when I try to load a sparse file via ext4load, I am getting the error message
'invalid extent'
After a deeper look in the code, it seems to be an issue in the function ext4fs_get_extent_block in fs/ext4/ext4_common.c:
The file starts with 1k of zeros. The blocksize is 1024. So the first extend block contains the following information:
eh_entries: 1
eh_depth: 1
ei_block 1
When the upper layer (ext4fs_read_file) asks for fileblock 0, we are running in the 'invalid extent' error message.
For me it seems, that the code is not prepared for handling a sparse block at the beginning of the file. The following change, solved my problem:
I am really not an expert in ext4 filesystems. Can somebody please have a look at this issue and give me a feedback, if I am totally wrong or not?
Test cases are:
1) basic link creation, verify it can be followed
2) chained links, verify it can be followed
3) replace exiting file a with a link, and a link with a link. verify it
can be followed
4) create a broken link, verify it can't be followed
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
fs: ext4: Add support for the creation of symbolic links
Re-use the functions used to write/create a file, to support creation of a
symbolic link.
The difference with a regular file are small:
- The inode mode is flagged with S_IFLNK instead of S_IFREG
- The ext2_dirent's filetype is FILETYPE_SYMLINK instead of FILETYPE_REG
- Instead of storing the content of a file in allocated blocks, the path
to the target is stored. And if the target's path is short enough, no block
is allocated and the target's path is stored in ext2_inode.b.symlink
As with regulars files, if a file/symlink with the same name exits, it is
unlinked first and then re-created.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
[trini: Fix ext4 env code] Signed-off-by: Tom Rini <trini@konsulko.com>
fs: ext4: constify the buffer passed to write functions
There is no need to modify the buffer passed to ext4fs_write_file().
The memset() call is not required here and was likely copied from the
equivalent part of the ext4fs_read_file() function where we do need it.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
We need to make sure that file writes,file creation, etc. are properly
performed and do not corrupt the filesystem.
To help with this, introduce the assert_fs_integrity() function that
executes the appropriate fsck tool. It should be called at the end of any
test that modify the content/organization of the filesystem.
Currently only supports FATs and EXT4.
Signed-off-by: Jean-Jacques Hiblot <jjhiblot@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Stephen Warren [Wed, 30 Jan 2019 19:58:05 +0000 (12:58 -0700)]
fs: ext4: cache extent data
When a file contains extents, U-Boot currently reads extent-related data
for each block in the file, even if that data is located in the same
block each time. This significantly slows down loading of files that use
extents. Implement a very dumb cache to prevent repeatedly reading the
same block. Files with extents now load as fast as files without.
Note: There are many cases where read_allocated_block() is called. This
patch only addresses one of those places; all others still read redundant
data in any case they did before. This is a minimal patch to fix the
load command; other cases aren't fixed.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
v2018.01 commit e23eb942ad103f ("ARM: rmobile: Stop using
rcar-common/common.c on Gen3") removed
board/renesas/rcar-common/common.c from the build chain with the
reasoning that calling arch_preboot_os() is no longer needed.
However, it left the arch_preboot_os() in place. Get rid of it.
This is done in preparation of resurrecting rcar-common/common.c.
NOTE: The three removed header includes (io.h, sys_proto.h, rcar-mstp.h)
are in direct relationship with the dropped arch_preboot_os() hook. The
other headers (common.h, rmobile.h) are going to be needed by pretty
much anything that is going to appear in the rcar common code. So, keep
the two in place.
Marek Vasut [Sat, 30 Mar 2019 06:22:09 +0000 (07:22 +0100)]
net: sh_eth: Initialize PHY in probe() once
Reset and initialize the PHY once in the probe() function rather than
doing it over and over again is start() function. This requires us to
keep the clock enabled while the driver is in use. This significantly
reduces the time between transfers as the PHY doesn't have to restart
autonegotiation between transfers, which takes forever.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Joe Hershberger <joe.hershberger@ni.com>
Marek Vasut [Mon, 4 Mar 2019 21:29:30 +0000 (22:29 +0100)]
pinctrl: renesas: Add TDSEL fixup for H2/E2 ES1.0 SoCs
Linux 5.0, commit 1c163f4c7b3f621efff9b28a47abb36f7378d783,
has a TDSEL fix for R8A7790 H2 and R8A7794 E2 SoCs, implement
similar fix for U-Boot. The difference here is that the SoC
ES matching has to be implemented manually.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Marek Vasut [Mon, 4 Mar 2019 12:36:13 +0000 (13:36 +0100)]
clk: renesas: Add R8A77965 clock tables
Add clock tables for R8A77965 from Linux 5.0 , except for the
crit, R and Z clock, which are neither used nor supported by
the U-Boot clock framework yet.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Marek Vasut [Wed, 13 Mar 2019 20:09:49 +0000 (21:09 +0100)]
ARM: rmobile: Enable multi-DTB fit LZO compression
Enable LZO compression of the multi-DTB fitImages, since the U-Boot
with multiple DTs enabled is becoming quite large and the DTs can
be well compressed. The LZO compression saves almost 200 kiB on the
Salvator-X(S) and ULCB targets.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Marek Vasut [Fri, 8 Mar 2019 15:06:55 +0000 (16:06 +0100)]
lib: fdt: Allow LZO and GZIP DT compression in U-Boot
Add required Kconfig symbols, Makefile bits and macro fixes in a
few places to support LZO and DT compression in U-Boot. This can
save a lot of space with multi-DTB fitImages.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Marek Vasut [Wed, 13 Mar 2019 20:11:22 +0000 (21:11 +0100)]
lib: fdt: Allow enabling both LZO and GZIP DT compression
Allow enabling both LZO and GZIP DT compression in SPL and fix a
bug where if the GZIP decompression failed, the LZO decompression
would not even be attempted.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com>
Marek Vasut [Thu, 18 Oct 2018 16:38:05 +0000 (18:38 +0200)]
ARM: renesas: Save boot parameters passed in by ATF
The ATF can pass additional information via the first four registers,
x0...x3. The R-Car Gen3 with mainline ATF, register x1 contains pointer
to a device tree with platform information. Save these registers for
future use.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Marek Vasut [Tue, 5 Mar 2019 03:25:55 +0000 (04:25 +0100)]
lib: fdt: Split fdtdec_setup_memory_banksize()
Split fdtdec_setup_memory_banksize() into fdtdec_setup_memory_banksize_fdt(),
which allows the caller to pass custom blob into the function and the
original fdtdec_setup_memory_banksize(), which uses the gd->fdt_blob. This
is useful when configuring the DRAM properties from a FDT blob fragment
passed in by the firmware.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Marek Vasut [Tue, 5 Mar 2019 03:25:54 +0000 (04:25 +0100)]
lib: fdt: Split fdtdec_setup_mem_size_base()
Split fdtdec_setup_mem_size_base() into fdtdec_setup_mem_size_base_fdt(),
which allows the caller to pass custom blob into the function and the
original fdtdec_setup_mem_size_base(), which uses the gd->fdt_blob. This
is useful when configuring the DRAM properties from a FDT blob fragment
passed in by the firmware.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Cc: Simon Glass <sjg@chromium.org> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Marek Vasut [Tue, 12 Mar 2019 03:00:09 +0000 (04:00 +0100)]
spl: ymodem: Move GZ handling out of YModem session
In case the gunzip() call fails, it will print an error message.
If that happens within the YModem session, the error message will
not be displayed and would be useless. Move the gunzip() call out
of the YModem session to make those possible error messages visible.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Tom Rini <trini@konsulko.com>
Adam Ford [Wed, 3 Apr 2019 13:41:56 +0000 (08:41 -0500)]
usb: ehci-mx6: Use common code to extract dr_mode
There exists code in drivers/common/common.c to read the dr_mode
from the device tree. This patch converts this driver to use that
function to initialize the driver.
Drop the counter, it has no meaning other than being the order in which
the interface is found; the name assigned to the USB host controller
interface is a better indicator.
Example of the original output:
> USB0: USB EHCI 1.10
> scanning bus 0 for devices... 2 USB Device(s) found
> scanning usb for storage devices... 1 Storage Device(s) found
Patched output:
> Bus usb@ee080100: USB EHCI 1.10
> scanning bus usb@ee080100 for devices... 2 USB Device(s) found
> scanning usb for storage devices... 1 Storage Device(s) found
Stefan Roese [Wed, 27 Mar 2019 10:20:19 +0000 (11:20 +0100)]
net: macb: Add small delay after link establishment
I've noticed that the first ethernet packet after PHY link establishment
is not tranferred correctly most of the time on my AT91SAM9G25 board.
Here I usually see a timeout of a few seconds, which is quite
annoying.
Adding a small delay (10ms in this case) after the link establishment
helps to solve this problem. With this patch applied, this timeout
on the first packet is not seen any more.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Wenyou Yang <wenyou.yang@atmel.com> Cc: Eugen Hristev <eugen.hristev@microchip.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Claudiu Beznea [Mon, 25 Mar 2019 10:33:56 +0000 (10:33 +0000)]
pinctrl: at91: add option to use drive strength bits
SAM9X60 uses high and low drive strengths. To implement this, in
at91_pinctrl_mux_ops::set_drivestrength we need bit numbers of
drive strengths (1 for low, 2 for high), thus change the code to
allow the usage of drive strength bit numbers.
Stefan Roese [Tue, 2 Apr 2019 08:57:27 +0000 (10:57 +0200)]
arm: at91: Add gardena-gateway-at91sam support
The GARDENA smart Gateway boards are equipped with an Atmel / Microchip
AT91SAM9G25 SoC and with 128 MiB of RAM and 256 MiB of NAND storage.
This patch adds support for this board including SPL support. Therefore
the AT91Boostrap is not needed on this platform any more.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Andreas Bießmann <andreas@biessmann.org> Cc: Eugen Hristev <eugen.hristev@microchip.com> Reviewed-by: Heiko Schocher <hs@denx.de>
Stefan Roese [Tue, 2 Apr 2019 08:57:25 +0000 (10:57 +0200)]
arm: at91: siemens: Add support to generate combined SPL+U-Boot image
This patch adds the necessary defines to the Siemens AT91SAM based
boards (smartweb, corvus and taurus) to generate the combined binary
image with SPL and main U-Boot image combined (u-boot-with-spl.bin).
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Andreas Bießmann <andreas@biessmann.org> Cc: Eugen Hristev <eugen.hristev@microchip.com> Reviewed-by: Heiko Schocher <hs@denx.de>
Tested on the taurus board: Tested-by: Heiko Schocher <hs@denx.de>
Stefan Roese [Wed, 3 Apr 2019 13:24:50 +0000 (15:24 +0200)]
Makefile: Add Kconfig option CONFIG_SPL_IMAGE to select the SPL binary
This patch adds the CONFIG_SPL_IMAGE option to select the SPL image that
shall be used to generate the combined SPL + U-Boot image. The default
value is the current value "spl/u-boot-spl.bin".
This patch also sets CONFIG_SPL_IMAGE to "spl/boot.bin" for AT91 targets
which use SPL NAND support (boot from NAND). For these build targets the
combined image "u-boot-with-spl.bin" is now automatically generated and
can be programmed into NAND as one single image (vs. SPL image and U-Boot
as 2 separate images).
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Andreas Bießmann <andreas@biessmann.org> Cc: Eugen Hristev <eugen.hristev@microchip.com>
Stefan Roese [Tue, 2 Apr 2019 08:57:23 +0000 (10:57 +0200)]
Makefile.spl: Move generated AT91SAM NAND image boot.bin to spl directory
This patch moves the AT91SAM NAND booting SPL image "boot.bin" which
includes the ECC values from the root directory into the spl directory,
where all SPL related images are located.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Andreas Bießmann <andreas@biessmann.org> Cc: Eugen Hristev <eugen.hristev@microchip.com> Reviewed-by: Heiko Schocher <hs@denx.de>
Tested on the taurus board: Tested-by: Heiko Schocher <hs@denx.de>
Stefan Roese [Tue, 2 Apr 2019 08:57:22 +0000 (10:57 +0200)]
arm: at91: arm926ejs/u-boot-spl.lds: Add _image_binary_end to SPL lds
This patch adds _image_binary_end to the SPL linker script. This will be
used be the upcoming GARDENA AT91SAM based platform, which uses DT in
SPL and configures CONFIGURE_SPL_SEPARATE_BSS.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Andreas Bießmann <andreas@biessmann.org> Cc: Eugen Hristev <eugen.hristev@microchip.com> Reviewed-by: Heiko Schocher <hs@denx.de>
Stefan Roese [Wed, 3 Apr 2019 05:37:40 +0000 (07:37 +0200)]
arm: at91: Enable watchdog support
This patch enables and starts the watchdog on the AT91 platform if
configured. The WD timeout value is read in the AT91 WD device driver
from the DT, using the "timeout-sec" DT property. If not provided in
the DT, the default value of 2 seconds is used.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Andreas Bießmann <andreas@biessmann.org> Cc: Eugen Hristev <eugen.hristev@microchip.com>
Stefan Roese [Wed, 3 Apr 2019 05:37:05 +0000 (07:37 +0200)]
arm: at91: Remove CONFIG_AT91_HW_WDT_TIMEOUT
This patch removes the CONFIG_AT91_HW_WDT_TIMEOUT as its not needed any
more. The WD timeout value can be provided via the "timeout-sec" DT
property. If not provided this way, the default value of 2 seconds will
be used.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Andreas Bießmann <andreas@biessmann.org> Cc: Eugen Hristev <eugen.hristev@microchip.com>
Stefan Roese [Tue, 2 Apr 2019 08:57:19 +0000 (10:57 +0200)]
watchdog: at91sam9_wdt: Fix WDT setup in at91_wdt_start()
This patch fixes the timer register setup in at91_wdt_start() to
correctly configure the register again. The input timeout value is
now in milli-seconds instead of seconds with the new watchdog API.
Make sure to take this into account and only use a max timeout
value of 16 seconds as appropriate for this SoC.
Also the check against a lower timeout value than 0 is removed. This
check makes no sense, as the timeout value is unsigned.
Signed-off-by: Stefan Roese <sr@denx.de> Reported-by: Heiko Schocher <hs@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Andreas Bießmann <andreas@biessmann.org> Cc: Eugen Hristev <eugen.hristev@microchip.com> Reviewed-by: Heiko Schocher <hs@denx.de>
Tested on the taurus board: Tested-by: Heiko Schocher <hs@denx.de>
Stefan Roese [Tue, 2 Apr 2019 08:57:18 +0000 (10:57 +0200)]
watchdog: Handle SPL build with watchdog disabled
This patch adds some checks, so that the watchdog can be enabled in main
U-Boot proper but can be disabled in SPL.
This will be used by some AT91SAM based boards, which might enable the
watchdog in the main U-Boot proper and not in SPL. It will be enabled in
SPL by default there, so no need to configure it there. This approach
saves some space in SPL.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Andreas Bießmann <andreas@biessmann.org> Cc: Eugen Hristev <eugen.hristev@microchip.com> Reviewed-by: Heiko Schocher <hs@denx.de>
Tested on the taurus board: Tested-by: Heiko Schocher <hs@denx.de>
Stefan Roese [Wed, 3 Apr 2019 13:24:19 +0000 (15:24 +0200)]
serial: atmel_usart: Use fixed clock value in SPL version with DM_SERIAL
This patch adds an alterative SPL version of atmel_serial_enable_clk().
This enables the usage of this driver without full clock support (in
drivers and DT nodes). This saves some space in the SPL image.
Please note that this fixed clock support is only added to the SPL code
in the DM_SERIAL part of this file. All boards not using SPL & DM_SERIAL
should not be affected.
This patch also introduces CONFIG_SPL_UART_CLOCK for the fixed UART
input clock. It defaults to 132096000 for ARCH_AT91 but can be set to
a different value if needed.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Andreas Bießmann <andreas@biessmann.org> Cc: Eugen Hristev <eugen.hristev@microchip.com>
Stefan Roese [Tue, 2 Apr 2019 08:57:16 +0000 (10:57 +0200)]
arm: at91: spl_at91.c: Call spl_early_init() if OF_CONTROL is enabled
This patch adds a call to spl_early_init() to board_init_f() which is
needed when CONFIG_SPL_OF_CONTROL is configured. This is necessary for
the early SPL setup including the DTB setup for later usage.
Please note that this call might also be needed for non SPL_OF_CONTROL
board, like the smartweb target. But smartweb fails to build with this
call because its binary grows too big. So I disabled it for these kind
of targets for now.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Heiko Schocher <hs@denx.de> Cc: Andreas Bießmann <andreas@biessmann.org> Cc: Eugen Hristev <eugen.hristev@microchip.com> Reviewed-by: Heiko Schocher <hs@denx.de>
Tested on the taurus board: Tested-by: Heiko Schocher <hs@denx.de>
Alexander Dahl [Fri, 22 Mar 2019 13:25:54 +0000 (14:25 +0100)]
ARM: at91: sama5d2: Wrap cpu detection to fix macb driver
When introducing the SAMA5D27 SoCs, the SAMA5D2 series got an additional
chip id. The check if the cpu is sama5d2 was changed from a preprocessor
definition (inlining a call to 'get_chip_id()') to a C function,
probably to not call get_chip_id twice?
That however broke a check in the macb ethernet driver. That driver is
more generic and also used for other platforms. I suppose this solution
was implemented to use it in 'gem_is_gigabit_capable()', without having
to stricly depend on the at91 platform:
That only works as long as cpu_is_sama5d2 is a preprocessor definition.
(The same is still true for sama5d4 by the way.) So this is a straight
forward fix for the workaround.
The not working check on the SAMA5D2 CPU lead to an issue on a custom
board with a LAN8720A ethernet phy connected to the SoC:
Jagan Teki [Mon, 8 Apr 2019 20:27:54 +0000 (01:57 +0530)]
arm: sunxi: Enable DM_MMC on required SoCs
Enabling DM_MMC is forcing CONFIG_BLK=y so if any board which uses
SCSI must need to enable DM_SCSI otherwise SCSI reads on that particular
target making invalid reading to the disk drive.
Allwinner platform do support SCSI on A10, A20 and R40 SoC's out of
these only A10 have DM_SCSI enabled. So enabling DM_MMC on A20, R40
would eventually end-up with scsi disk read failures like [1]
So, enable DM_MMC in all places of respective SoC's instead of enabling
them globally to Allwinner platform.
Now, DM_MMC is enabled in Allwinner SoC's except A20 and R40.
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