Tom Rini [Thu, 24 Sep 2020 12:33:47 +0000 (08:33 -0400)]
Merge tag 'xilinx-for-v2021.01' of https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze into next
Xilinx changes for v2021.01
arm64:
- Support for bigger U-Boot images compiled with PIE
microblaze:
- Extend support for LE/BE systems
zynqmp:
- Refactor silicon ID detection code with using firmware interface
- Add support for saving variables based on bootmode
zynqmp-r5:
- Fix MPU mapping and defconfig setting.
xilinx:
- Minor driver changes: names alignment
- Enable UBIFS
- Minor DT and macros fixes
- Fix boot with appended DT
- Fix distro boot
cmd:
- pxe: Add fixing for platforms with manual relocation support
clk:
- fixed_rate: Add DM flag to support early boot on r5
fpga:
- zynqmppl: Use only firmware interface and enable SPL build
serial:
- uartlite: Enable for ARM systems and support endians
mmc:
- zynq: Fix indentation
net:
- gem: Support for multiple phys
- emac: Fix 64bit support and enable it for arm64
kconfig:
- Setup default values for Xilinx platforms
- Fix dependecies for Xilinx drivers
- Source board Kconfig only when platform is enabled
- Fix FPGA Kconfig entry with SPL
- Change some defconfig values
Tom Rini [Thu, 24 Sep 2020 12:30:25 +0000 (08:30 -0400)]
Merge branch 'mpc85xx-for-v2021.01' into next
- Add DM_SPI, DM_SPI_FLASH support for powerpc platforms
- Add DM_ETH support on P1010RDB, P1020RDB, P2020RDB
- Remove some un-maintained powerpc platforms
- Add USB_STORAGE support in config
Ran Wang [Tue, 30 Jun 2020 05:08:34 +0000 (13:08 +0800)]
configs: powerpc: add usb (host) mass storage support
commit 0cfccb54014b ("configs: Resync with savedefconfig")
removed CONFIG_USB_STORAGE from some powerpc platforms' defconfig
files, whicih would block the use case of system loading rootfs
from USB drives, add them back.
Signed-off-by: Ran Wang <ran.wang_1@nxp.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
The info of fixed-link PHY is described in DT node instead of
getting from MII, so detect the fixed-link PHY DT node first,
if it doesn't exist then probe the MII.
net: tsec: convert to use DM_MDIO when DM_ETH enabled
For the platforms on which the eTSEC driver uses DM_ETH, convert its
MDIO controller code to also use DM_MDIO.
Note that for handling the TBI PHY (the MAC PCS for SGMII), we still
don't register a udevice for it, since we can drive it locally and there
is no point in doing otherwise.
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
[Reworked to fix gazerbeam config] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
net: fsl_mdio: Correct the MII management register block address
The MII management register block offset is different between
gianfar and etsec2 compatible devices, this patch is to fix
this issue by adding driver data for different compatible
string.
Vladimir Oltean [Thu, 16 Jul 2020 10:09:09 +0000 (18:09 +0800)]
configs: enable DM_MDIO for LS1021A-TWR and LS1021A-TSN
The tsec driver now requires DM_MDIO when DM_ETH is enabled. To avoid
build errors, enable DM_MDIO in these boards' configs before we actually
add DM_MDIO support to tsec.
Vladimir Oltean [Thu, 16 Jul 2020 10:09:08 +0000 (18:09 +0800)]
phy: make phy_connect_fixed work with a null mdio bus
It is utterly pointless to require an MDIO bus pointer for a fixed PHY
device. The fixed.c implementation does not require it, only
phy_device_create. Fix that.
pxe sub commands need to be manually relocated for architectures which
enables MANUAL_RELOC as Microblaze.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Michal Simek [Mon, 14 Sep 2020 14:33:46 +0000 (16:33 +0200)]
xilinx: r5: Fix MPU setting for R5
Map all resource for R5 to operate properly.
The patch is done based on the commit 23f7b1a77602 ("armv7R: K3: am654:
Enable MPU regions") which also map the whole 4GB at first and then change
mapping for DDR.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 3 Sep 2020 09:23:39 +0000 (11:23 +0200)]
spl: Kconfig: Record proper dependency for SPL_ATF
ATF support was all the time based on FIT image support but this dependency
is not recorded anywhere.
For !SPL_FIT && SPL_ATF there is compilation error:
common/spl/spl.c: In function 'board_init_r':
common/spl/spl.c:689:26: error: 'struct spl_image_info' has no member named 'fdt_addr'
689 | spl_fixup_fdt(spl_image.fdt_addr);
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Tue, 8 Sep 2020 11:11:02 +0000 (13:11 +0200)]
xilinx: Disable CONFIG_EFI_LOADER_BOUNCE_BUFFER for ZynqMP/Versal
Both SOCs shouldn't have any problem with 64bit dma accesses. Also with PIE
enabled when u-boot is placed above 4GB without any memory mapped below 4GB
address space efi_memory_init() call is failing due to missing memory node.
For this two reason disable this option for ZynqMP and Versal.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Fri, 4 Sep 2020 14:21:47 +0000 (16:21 +0200)]
xilinx: common: Do not save fdt_blob to bss section
For SPL flow without specifying address for DT loading DTB is automatically
appended behind U-Boot code. Specifically _end symbol is used. Just behind
it there is place for bss section.
It means if early code is using static variable and there is a write to
this variable DTB file is corrupted if variable is located between DTB
start and end.
In this particular case offset of this variable from bss section start is
very small (0x40) that's why DT is currupted which breaks this boot flow.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 30 Jul 2020 11:37:49 +0000 (13:37 +0200)]
xilinx: zynqmp: Add support for saving variables
Enabling saving variables to MMC(FAT), NAND, SPI based on primary bootmode.
Maybe that logic can be tuned for more complicated use cases and better
tested for different bootmodes.
Tested on zcu104 to SD(FAT) and JTAG(NOWHERE).
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Wed, 5 Aug 2020 10:41:35 +0000 (12:41 +0200)]
xilinx: zynqmp: Remove one static variable
There is no reason to have name variable saved in BSS section when it
doesn't need to be really used. That's why remove static from variable
definition and use strdup() to duplicate string with exact size from malloc
area instead.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Ibai Erkiaga [Tue, 4 Aug 2020 22:17:31 +0000 (23:17 +0100)]
xilinx: zynqmp: refactor silicon name function
Current algorithm used to get the silicon name is bit complicated and
hard to follow. Updated to use more straightforward mechanism based on
the Device ID code table (Table 1-2). The full IDCODE register is used
(except device revision bits [31:28]) to get the device name and IDCODE2
value is used for identifying the variant.
Additionally to make the algorithm bit more clear it also save some space
as the devices table is slightly bit smaller.
Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
flush_cache() arguments are not type casted to take care of 64 bit
systems. Use phys_addr_t to type cast for it to work properly for 32 bit
and 64 bit systems.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
net: xilinx: axi_emac: Fix dma descriptors for 64bit and compilation warnings
There are compilation warnings showing up when we compile AXI ethernet
driver for 64bit architectures. Fix them, so that it works on both 32
and 64 bit architectures.
DMA descriptors are not taking care of 64bit addresses. To fix it,
change axidma_bd members as below:
and update next_desc and buf_addr with lower 32 bits of the addresses,
update next_desc_msb and buf_addr_msb with upper 32 bits of the 64bit
addresses.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Saeed Nowshadi [Tue, 4 Aug 2020 06:24:04 +0000 (23:24 -0700)]
arm64: zynqmp: Add device tree node for 2nd mux on I2C1 bus
There is 2nd pca9548 mux on I2C1 bus that controls SFP0, SFP1, and QSFP1
ports. Channel 0 and 1 are connected to J287 connector for SFP0 & SFP1, and
channel 2 is connected to J288 connector for QSFP1.
Signed-off-by: Saeed Nowshadi <saeed.nowshadi@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
T Karthik Reddy [Fri, 14 Aug 2020 09:02:15 +0000 (03:02 -0600)]
serial: uartlite: Add support to work with any endianness
This endinness changes are taken from linux uartlite driver.
Reset TX fifo in control register and check TX fifo empty
flag in lower byte of the status register to detect if it
is a little endian system. Based on this check, program the
registers with le32 or be32 through out the driver.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
We will format the partition from linux and copy some files and access
from uboot later.
First thing, in linux config disable CONFIG_MTD_SPI_NOR_USE_4K_SECTORS.
this is required as ubifs expects min LEB size as 15*1024 bytes.
Use below commands in linux to format "images" partition with ubifs.
To access this ubifs partition from uboot, run below commands.
(Don't forget to probe device before, e.g. sf probe 0 0 0)
setenv mtdids "nor0=nor0"
setenv mtdparts "mtdparts=nor0:16m(boot),112m(images)"
ubi part images
ubifsmount ubi0:images
make sure we match "mtdparts" to whatever is given in dt w.r.t partition
sizes.
"mtdparts" command will list the mtd partitions in u-boot.
Once ubifs is mounted, we can use "ubifsls" to list the files in that
partition and use "ubifsload <addr> <filename>" to load files from ubifs
partition to DDR.
Reading information about mtd layout from DT is not supported.
Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 20 Aug 2020 12:02:47 +0000 (14:02 +0200)]
board: xilinx: Enable changing default DTB pick up address
U-Boot on xilinx boards is checking one address where DTB can be placed as
the first location for DTB. Originally this code was developed for Versal
where QEMU was putting generated DTB for U-Boot to use.
The patch enables changing this address which is necessary for cases where
default address is pointing to location (DDR) which is not present. The
access to this location can cause exception.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
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