Patrick Delaunay [Wed, 10 Apr 2019 12:09:26 +0000 (14:09 +0200)]
stm32mp1: ram: add support for LPDDR2/LPDDR3
Manage power supply configuration for board using stpmic1
with LPDDR2 or with LPDDR3:
+ VDD_DDR1 = 1.8V with BUCK3 (bypass if possible)
+ VDD_DDR2 = 1.2V with BUCK2
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Patrick Delaunay [Wed, 10 Apr 2019 12:09:24 +0000 (14:09 +0200)]
ARM: dts: stm32mp1: DDR config v1.44
Update DDR configuration with the latest update:
- PUBL_regs: DXnGCR[0]= according to ddr_width to disable Byte
lane 2/3 in 16bit
- fix LPDDR2/3 timing_calc to step RL/WL in relaxed
timings mode
- remove LPDDR3 RL3 (optional) support vs MR0[7]
because MR0[7] can't be read instead always apply
worse RL/WL for LPDDR3 when freq < 166MHz)
- change MR3 to 48ohm drive for LPDDR2/3
- change default ZPROG[7:4] = 0x1 for LPDDR2/3 ,
'0' is not allowed even when ODT not used
- use DQSTRN for LPDDR2/3 (it was not set in PIR)
- LPDDR3: set dqsge/dwsgx gate extension to 2,2
like LPDDR2
-DDRCTRL.dfitmg0:
+ for LPDDR3 tphy_wrlat = WL (as LPDDR2)
+ improvement for relaxed mode vs RL/Wl at corner case.
For example @533MHz RL/WL (relaxed) = 9/5 for LPDDR2/3
and correction to MR2 accordingly
- DDR_PCFGQOS1_1: port1 timeout relaxed from 0x00 to 0x40,
for LTDC.
- DDR_PCFGWQOS0_0: change vpr level from
11 to 12 in order to include the CPU on
the variable priority queue.
- DDR_SCHED: fix to consider 13 levels (13 levels - 1 = 0xC)
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Patrick Delaunay [Thu, 18 Apr 2019 15:32:51 +0000 (17:32 +0200)]
serial: stm32: remove watchog reset in debug putc
For STM32MP, the watchdog is based on DM and the function watchod_reset
call the function uclass_get_device(UCLASS_WDT) to found the driver
associated IWDG2.
As this reset is not mandatory in debug putc (the uart fifo will be
empty after some us), we can simplify the code by removing this call.
And this patch avoid issue when putc is called before initialization
of DM core, before the parsing of the device tree parsing and each
node bound to driver; that also avoid memory leak.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Patrick Delaunay [Thu, 18 Apr 2019 15:32:46 +0000 (17:32 +0200)]
armv7: timer: init timer with bootstage
In initf_bootstage() we call bootstage_mark_name() which ends up calling
timer_get_us() before timer_init(); that cause crash for stm32mp1.
This patch solve the issue without changing the initialization sequence.
See also commit 97d20f69f53e ("Enable CONFIG_TIMER_EARLY with bootstage")
for other solution when DM is activated for TIMER.
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Patrick Delaunay [Thu, 18 Apr 2019 15:32:44 +0000 (17:32 +0200)]
mkimage: change stm32image header to manage binary information
To get more information from STM32 Header about the generated binary,
we will add a new byte with the following field:
replace padding byte 255 with 0x00 for "U-Boot"
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Nicolas Le Bayon [Thu, 18 Apr 2019 15:32:43 +0000 (17:32 +0200)]
i2c: stm32f7: improve loopback in timing algorithm
This avoids useless loops inside the I2C timing algorithm.
Actually, we support only one possible solution per prescaler value.
So after finding a solution with a prescaler, the algorithm can
switch directly to the next prescaler value.
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Reviewed-by: Patrick DELAUNAY <patrick.delaunay@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Nicolas Le Bayon [Thu, 18 Apr 2019 15:32:42 +0000 (17:32 +0200)]
i2c: stm32f7: Fix SDADEL minimum formula
It conforms with Reference Manual I2C timing section.
Signed-off-by: Nicolas Le Bayon <nicolas.le.bayon@st.com> Reviewed-by: Patrick DELAUNAY <patrick.delaunay@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Patrick Delaunay [Thu, 18 Apr 2019 15:32:40 +0000 (17:32 +0200)]
stm32mp1: psci: add synchronization with ROM code
Use SGI0 interruption and TAMP_BACKUP_MAGIC_NUMBER
to synchronize the core1 boot sequence requested by
core0 in psci_cpu_on():
- a initial interruption is needed in ROM code after
RCC_MP_GRSTCSETR_MPUP1RST (psci_cpu_off)
- the ROM code set to 0 the 2 registers
+ TAMP_BACKUP_BRANCH_ADDRESS
+ TAMP_BACKUP_MAGIC_NUMBER
when magic is not egual to
BOOT_API_A7_CORE0_MAGIC_NUMBER
This patch solve issue for cpu1 restart in kernel.
echo 0 > /sys/devices/system/cpu/cpu1/online
echo 1 > /sys/devices/system/cpu/cpu1/online
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Patrick Delaunay [Thu, 18 Apr 2019 15:32:36 +0000 (17:32 +0200)]
stm32mp1: Move config SYS_MALLOC_LEN to Kconfig
This patch moves the the config SYS_MALLOC_LEN to
Kconfig as it is already done for zynq arch in
commit 01aa5b8f0503 ("Kconfig: Move config
SYS_MALLOC_LEN to Kconfig for zynq")
Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
Tom Rini [Wed, 22 May 2019 12:32:24 +0000 (08:32 -0400)]
Merge git://git.denx.de/u-boot-fsl-qoriq
Changes from rc2 tag
- Support PCIe Gen4 driver of the Mobiveil IP
- NXP LS1028A SoC and platform support
- Few SPI related config updates
- Distinguish the ecc val by chassis version and move the ecc addr to dts
- sp805 watchdog support
esbc_validate command will not be executed if “load” command for its
header fails and will further execute the source command for bootscript,
without its validation and boot process continues.
To halt the boot process in case secure boot header is not loaded
successfully, esbc_validate command is invoked separately after “load”
command. The secure boot validation of the bootscript header will fail
(if header is not loaded) and halts the boot process, which prevent source
command from execution.
LS1028AQDS Development System is a high-performance
computing, evaluation, and development platform that supports
LS1028A QorIQ Architecture processor.
LS1028A is an ARMv8 implementation. LS1028ARDB is an evaluation
platform that supports the LS1028A family SoCs. This patch add basic
support of the platform.
pci: Add PCIe Gen4 controller driver for NXP Layerscape SoCs
Add PCIe Gen4 driver for the NXP Layerscape SoCs. This PCIe
controller is based on the Mobiveil IP, which is compatible
with the PCI Express™ Base Specification, Revision 4.0.
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Bao Xiaowei <Xiaowei.Bao@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
configs: ls1046: Update mtd-id for QSPI nor in mtdparts variable
Update mtd-id for QSPI nor due to change introduced in mtd/spi in
linux 5.0. commit 84d043185dbe
("spi: Add a driver for the Freescale/NXP QuadSPI controller")
This modification is only for linux kernel version >= 5.0. To use
bootargs for kernel < 5.0, use the following bootargs
CONFIG_BOOTARGS="console=ttyS0,115200 root=/dev/ram0
earlycon=uart8250,mmio,0x21c0500
mtdparts=1550000.quadspi:2m(uboot),14m(free)"
Tom Rini [Tue, 21 May 2019 11:12:46 +0000 (07:12 -0400)]
Merge tag 'video-for-2019.07-rc3' of git://git.denx.de/u-boot-video
- update for using splashfile instead of location->name
when loading the splash image from a FIT
- updates for loading internal and external splash data from FIT
- DM_GPIO/DM_VIDEO migration for mx53 cx9020 board
- fix boot issue on mx6sabresd board after DM_VIDEO migration
- increase the max preallocated framebuffer BPP to 32 in ipuv3
driver to prepare for configurations with higher color depth
- allow to use vidconsole_put_string() in board code for text
output on LCD displays
Mario Six [Fri, 29 Mar 2019 09:18:09 +0000 (10:18 +0100)]
gdsys: mpc8308: Don't use manual RAM config if RAM driver is active
The "manual" RAM configuration should not be used if the DM RAM driver
is active, hence, disable the code if the CONFIG_MPC83XX_SDRAM config
variable is defined.
Mario Six [Fri, 29 Mar 2019 09:18:05 +0000 (10:18 +0100)]
gdsys: Post ppc4xx removal cleanup
The ppc4xx architecture was removed, and with it several old gdsys 44x
boards, but some "debris" from these purged boards was left over.
This patch removes these remnants (mostly entries in Makefiles, some now
superfluous data structures and some now obsolete config variables from
the whitelist).
Mario Six [Mon, 28 Jan 2019 08:45:57 +0000 (09:45 +0100)]
i2c: ihs: Get rid of fpgamap
Since the IHS I2C driver want upstream, the surrounding infrastructure
has changed quite a bit (notably, the fpgamap driver was replaced with a
regmap driver).
Update the driver to work with these changes.
Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Heiko Schocher <hs@denx.de>
Mario Six [Mon, 28 Jan 2019 08:33:39 +0000 (09:33 +0100)]
powerpc: Simplify processor.h
Lots of stuff in processor.h was taken verbatim from the Linux kernel.
It was never synced, so most of it was removed or changed in the kernel
since it was imported.
Remove all the stuff that is unused in the current U-Boot sources;
should anybody feel the need to re-sync with the kernel, they can do it
later on.
Mario Six [Mon, 21 Jan 2019 08:18:23 +0000 (09:18 +0100)]
keymile: Factor out common includes again
Not that the Kconfig conversion of a lot of variables is done, we can
factor out the common include files for the keymile boards again (which
now contain hardly any #ifdef logic at all).
Mario Six [Mon, 21 Jan 2019 08:18:22 +0000 (09:18 +0100)]
keymile: Remove CONFIG_SYS_APP{1, 2}_{BASE, SIZE}
CONFIG_SYS_APP1_BASE, CONFIG_SYS_APP2_BASE, CONFIG_SYS_APP1_SIZE, and
CONFIG_SYS_APP2_SIZE are no longer used in the keymile config files
(they were used for setting values, which were converted to Kconfig
earlier in the series).
Mario Six [Mon, 21 Jan 2019 08:18:21 +0000 (09:18 +0100)]
mpc83xx: Use pre-defined asm functions
For a lot of inline assembly calls in the mpc8xxx and mpc83xx
directories, we already have convenient pre-defined helper functions,
but they're not used, resulting in hard-to-read code.
Use these helper functions where ever possible and useful.
Mario Six [Mon, 21 Jan 2019 08:18:20 +0000 (09:18 +0100)]
mpc83xx: Replace ppcDWstore with inline assembly
ppcDWstore/ppcDWload are hardly used by any board, but since they're
implemented in start.S, they're always present in every U-Boot image,
even if they're not needed.
Re-implement these fuctions in C with inline assembly, so that the
compiler can decide when to actually include them.
Mario Six [Mon, 21 Jan 2019 08:18:03 +0000 (09:18 +0100)]
mpc83xx: Migrate CONFIG_SYS_{BR, OR}*_PRELIM to Kconfig
Migrate the BR/OR settings to Kconfig. These must be known at compile
time, so cannot be configured via DT.
Configuration of this crucial variable should still be somewhat
comfortable. Hence, make its fields configurable in Kconfig, and
assemble the final value from these.
Mario Six [Mon, 21 Jan 2019 08:18:02 +0000 (09:18 +0100)]
sbc8349: Remove SDRAM functionality
The MPC8349EMDS configuration was the basis for the sbc8349, so it also
contains its SDRAM option.
Since
* the SDRAM has to be soldered onto the board,
* the sbc8349 never used the support, and
* the support never worked (see previous patch fixing it),
we can assume that the support on the sbc8349 is an artifact created by
copying the MPC8349EMDS config wholesome.
Hence, instead of creating a separate sbc8349 config that supports
SDRAM, we can remove the SDRAM option for this board.
Should it be needed in the future, it can be copied from the new
MPC8349EMDS_SDRAM board.
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