Because the mvpp2 driver now relies on the PHYLIB and
the external MDIO driver, configuring low level
SMI bus settings is redundant.
Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Reviewed-by: Stefan Chulski <stefanc@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Stefan Chulski [Mon, 3 May 2021 06:08:45 +0000 (08:08 +0200)]
net: mvpp2: add CP115 port1 10G/5G SFI support
1. Differ between Port1 RGMII and SFI modes in Netcomplex config.
2. Remove XPCS config from SFI mode.
Port1 doesn't XPCS domain, XPCS config should be removed.
Access to Port1 XPCS can cause stall.
3. Add Port1 MPCS configurations.
Signed-off-by: Stefan Chulski <stefanc@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
Tom Rini [Wed, 19 May 2021 15:50:25 +0000 (11:50 -0400)]
Merge tag 'xilinx-for-v2021.07-rc3' of https://source.denx.de/u-boot/custodians/u-boot-microblaze
Xilinx changes for v2021.07-rc3
ZynqMP:
- Syncup DT with Linux kernel
- Fix mmc mini configurations via DT
- Add pinctrl/psgtr description to DTs
- Add DTs for Kria boards
- Enable RTC and Time commands
U-Boot expects to be linked to a specific hard-coded address and to
be loaded to and run from that address. CONFIG_POSITION_INDEPENDENT
config lifts that restriction & allowing the code to be loaded to
and executed from almost any address.
As we enabled CONFIG_POSITION_INDEPENDENT, CONFIG_INIT_SP_RELATIVE
is enabled by default, where it will set the early stack pointer at
runtime by adding an offset value to &_bss_start. The offset value
is taken from SYS_INIT_SP_BSS_OFFSET.
SYS_INIT_SP_BSS_OFFSET offset should be large enough so that the
early malloc region, global data (gd), and early stack should fit.
With commit d8fabcc424bd ("arm64: versal: Increase SYS_MALLOC_F_LEN")
SYS_MALLOC_F_LEN is increased from 32KB to 1MB, so we need to
accommodate this space with SYS_INIT_SP_BSS_OFFSET. Hence increasing
SYS_INIT_SP_BSS_OFFSET to 1.5MB.
Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Acked-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Mon, 10 May 2021 14:02:15 +0000 (16:02 +0200)]
arm64: zynqmp: Add description for SOM/Kria boards
The patch contains several DT files for SOM platform.
Carrier card is sck-kv (KV260) revA/B. SMK-K26 is description for starter
kit which doesn't have EMMC populated. And SM-K26 is full som with EMMC.
Files are divided in this way to make sure that SOM can be plugged to
different carrier card and all peripherals on SOM (or defined by a spec) can
be used by U-Boot. Full DT for SOM+CC can be merged together as overlays.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Mon, 10 May 2021 12:55:34 +0000 (14:55 +0200)]
arm64: zynqmp: Add psgtr DT descriptions
Mainline kernel has psgtr driver that's why it is good to add description
to DT files. Some boards are just missing description for USB3 and sata.
zc1751-dc1 and p-a2197 are also missing clock descriptions for input
clocks.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 21 Jan 2021 10:26:55 +0000 (11:26 +0100)]
arm64: zynqmp: Add missing mio-bank properties to sdhci
Add missing xlnx,mio-bank property to sdhci node. Also add properties with
0 value to have it listed in case that files are copied to different
projects where default case doesn't need to be handled in the same way.
That's why explicitly list them too.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Now it results in 2 slave devices with same address (0x50)
on the I2C bus, making the communication un-reliable.
When ' i2c-mux-idle-disconnect' is in DT, after '1', the Mux
channel output is disconnected, making none of the channels
available to the I2C1. So, there is no question of having the
same addressed slave (0x50) present on the bus when we are doing '2'.
arm64: zynqmp: Add label to all GPIO lines for VCK190 SC
Add label to GPIO lines so the user-level applications can find any line
without knowing its physical path on System Controller on VCK190/VMK180.
These labels are describing EMIO gpio connection which depends on PL which
we normally don't describe but that's only way to go for now. Lately this
should be done out of this source code.
Signed-off-by: Saeed Nowshadi <saeed.nowshadi@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Saeed Nowshadi [Mon, 22 Mar 2021 18:58:38 +0000 (11:58 -0700)]
arm64: zynqmp: Add 'silabs,skip-recall' to DDR DIMM si570 clk node
The 'silabs,skip-recall' property prevents interruption in operation of
the clock while the driver is being probed. Without this property, the
DDR DIMM clk can cause a failure during Versal's boot.
Michal Simek [Tue, 9 Mar 2021 11:43:42 +0000 (12:43 +0100)]
arm64: zynqmp: Add missing silabs,skip-recall for si570 ref clk nodes
All si570 which are used for ps reference clock generation should contain
silabs,skip-recall property not to cause break on ps clock.
On Versal boards this will cause hang on Versal cpu when it is booted at
the same time with SC.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Tom Rini [Tue, 18 May 2021 15:10:00 +0000 (11:10 -0400)]
Merge tag 'efi-2021-07-rc3' of https://source.denx.de/u-boot/custodians/u-boot-efi
Pull request for efi-2021-07-rc3
Documentation:
* add a man-page for the size command
* add man-page for extension command to index
Bug fixes:
* avoid build failure due to missing SHA512 hardware acceleration
* correct error handling in TCG2 protocol
* don't let user disable capsule authentication
* correct reading directories via UEFI API
Masahisa Kojima [Thu, 13 May 2021 14:48:08 +0000 (23:48 +0900)]
lib: introduce HASH_CALCULATE option
Build error occurs when CONFIG_EFI_SECURE_BOOT or
CONFIG_EFI_CAPSULE_AUTHENTICATE is enabled,
because hash-checksum.c is not compiled.
Since hash_calculate() implemented in hash-checksum.c can be
commonly used aside from FIT image signature verification,
this commit itroduces HASH_CALCULATE option to decide
if hash-checksum.c shall be compiled.
Signed-off-by: Masahisa Kojima <masahisa.kojima@linaro.org> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Ilias Apalodimas [Tue, 11 May 2021 21:03:41 +0000 (00:03 +0300)]
efi_loader: Don't stop EFI subsystem init if installing TCG2 fails
Up to now we are stopping the EFI subsystem if a TPMv2 exists but the
protocol fails to install. Now that we've switched the config to 'default
y' the sandbox TPM fails, since it doesn't support all the required
capabilities of the protocol.
Not installing the protocol is not catastrophic. If the protocol fails
to install the PCRs will never be extended to the expected values, so
some other entity later in the boot flow will eventually figure it out
and take the necessary actions.
While at it fix a corner case were the user can see an invalid error
message when the protocol failed to install. We do have a tcg2_uninit()
which we call when the protocol installation fails. There are cases though
that this might be called before the configuration table is installed (e.g
probing the TPM for capabilities failed). In that case the user will see
"Failed to delete final events config table". So stop printing it since it's
not an actual failure , simply because the config table was never installed
in the first place.
In order to stop printing it make efi_init_event_log() and create_final_event()
cleanup themselves and only call tcg2_uninit() when the protocol installation
fails.
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Ilias Apalodimas [Mon, 10 May 2021 18:19:14 +0000 (21:19 +0300)]
efi_loader: Uninstall the TCG2 protocol if logging s-crtm fails
Instead of just failing, clean up the installed config table and
EventLog memory if logging an s-crtm event fails during the protocol
installation
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Eliminate label 'out:' by using return. Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Ilias Apalodimas [Mon, 10 May 2021 18:15:08 +0000 (21:15 +0300)]
efi_loader: Clean up tcg2 once in case of failure
efi_init_event_log() calls tcg2_uninit() in case of failure.
We can skip that since the function is called on efi_tcg2_register()
which also cleans up if an error occurs
Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Peng Fan [Wed, 28 Apr 2021 13:54:01 +0000 (21:54 +0800)]
efi_loader: loosen buffer parameter check in efi_file_read_int
This is same issue as https://bugzilla.redhat.com/show_bug.cgi?id=1733817,
but that fix was wrongly partial reverted.
When reading a directory, EFI_BUFFER_TOO_SMALL should be returned when
the supplied buffer is too small, so a use-case is to call
EFI_FILE_PROTOCOL.Read() with *buffer_size=0 and buffer=NULL to
obtain the needed size before doing the actual read.
So remove the check only for directory reading, file reading already
do the check by itself.
Fixes: db12f518edb0("efi_loader: implement non-blocking file services") Signed-off-by: Peng Fan <peng.fan@nxp.com> Cc: Stefan Sørensen <stefan.sorensen@spectralink.com> Tested-by: Peter Robinson <pbrobinson@gmail.com> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
efi_loader: capsule: Remove the check for capsule_authentication_enabled environment variable
The current capsule authentication code checks if the environment
variable capsule_authentication_enabled is set, for authenticating the
capsule. This is in addition to the check for the config symbol
CONFIG_EFI_CAPSULE_AUTHENTICATE. Remove the check for the environment
variable. The capsule will now be authenticated if the config symbol
is set.
Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org> Reviwed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
hash: Kconfig option for SHA512 hardware acceleration
Commit a479f103dc1c ("hash: Allow for SHA512 hardware implementations")
defined function definitions for hardware accelerated SHA384 and SHA512.
If CONFIG_SHA_HW_ACCEL=y, these functions are used.
We already have boards using CONFIG_SHA_HW_ACCEL=y but none implements the
new functions hw_sha384() and hw_sha512().
For implementing the EFI TCG2 protocol we need SHA384 and SHA512. The
missing hardware acceleration functions lead to build errors on boards like
peach-pi_defconfig.
Introduce a new Kconfig symbol CONFIG_SHA512_HW_ACCEL to control if the
functions hw_sha384() and hw_sha512() shall be used to implement the SHA384
and SHA512 algorithms.
Fixes: a479f103dc1c ("hash: Allow for SHA512 hardware implementations") Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
efi_loader: build warning in efi_tcg2_hash_log_extend_event
Building 32bit boards with the TCG2 protocol enabled leads to a build
warning due to a missing conversion.
lib/efi_loader/efi_tcg2.c:774:27:
error: cast to pointer from integer of different size
[-Werror=int-to-pointer-cast]
774 | ret = tcg2_create_digest((u8 *)data_to_hash, data_to_hash_len,
| ^
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Simon Glass [Fri, 7 May 2021 01:32:23 +0000 (19:32 -0600)]
Makefile: Handle building in a very old build directory
Versions of U-Boot before 2014.01 created a symlink from include/asm to
the architecture-specific header directory.
If an ARM board is build with that old version, then sandbox is built on
a more recent version (both with in-tree builds), the include/asm symlink
confuses the build system. It picks up the ARM headers when it should be
using the sandbox ones.
Since 2014 U-Boot has only created a symlink inside the include/asm/
directory and only for out-of-tree builds. So for in-tree builds it does
not expect to see an include/asm symlink. It is not removed by
'make mrproper'. It does show up with 'git status' but is easy enough to
miss.
Add include/asm to the files to remove with 'make mkproper'. For recent
U-Boot builds this has no effect, since include/asm is a directory, not a
file. If the include/asm symlink is there, it will be removed.
Reported-by: Marek Szyprowski <m.szyprowski@samsung.com> Signed-off-by: Simon Glass <sjg@chromium.org>
Igor Opaniuk [Thu, 6 May 2021 14:34:27 +0000 (17:34 +0300)]
psci: rename psci_features function
s/psci_features/request_psci_features/g for the case when both
ARCH_SUPPORT_PSCI=y and ARM_PSCI_FW=y, that leads to these
compilation issues:
drivers/firmware/psci.c:69:12: error: conflicting types for 'psci_features'
69 | static int psci_features(u32 psci_func_id)
| ^~~~~~~~~~~~~
In file included from drivers/firmware/psci.c:23:
./arch/arm/include/asm/system.h:548:5: note: previous declaration of 'psci_features' was here
548 | s32 psci_features(u32 function_id, u32 psci_fid);
| ^~~~~~~~~~~~~
Tested-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reported-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Fixes: b7135b034f ("psci: add features/reset2 support") Signed-off-by: Igor Opaniuk <igor.opaniuk@foundries.io>
Python3 taken from the PATH causes build issues when pylibfdt bindings are
generated with Yocto SDK.
Python3 provided as a part of SDK is not compatible with host Python3,
therefore binding build breaks with following errors:
scripts/dtc/pylibfdt/libfdt_wrap.c:154:11: fatal error: Python.h: No such file or directory
154 | # include <Python.h>
| ^~~~~~~~~~
Do not enforce the python3 from the PATH and make it conditionally-assigned
so it can be overridden from outside of build system. Keep the default
assignment to point to version that is taken from the PATH.
Similar fix has been introduced in b48bfc74ee ("tools: allow to override
python"), where conditional assignment is used for python executable to
address similar build errors.
Signed-off-by: Andrey Zhizhikin <andrey.zhizhikin@leica-geosystems.com> Cc: Simon Glass <sjg@chromium.org> Fixes: e91610da7c ("kconfig: re-sync with Linux 4.17-rc4") Reviewed-by: Simon Glass <sjg@chromium.org>
- Add base support for Marvell OcteonTX2 CN9130 DB (mostly done
by Kostya)
- Sync Armada 8k MMU setup with Marvell version (misc Marvell
authors)
- spi: kirkwood: Some fixes especially for baudrate generation
(misc Marvell authors)
- mvebu: x530: Reduce SPL image size (Stefan)
- Rename "rx_training" to "mvebu_comphy_rx_training" (Stefan)
Bin Meng [Thu, 13 May 2021 08:46:18 +0000 (16:46 +0800)]
riscv: Group assembly optimized implementation of memory routines into a submenu
Currently all assembly optimized implementation of memory routines
show up at the top level of the RISC-V architecture Kconfig menu.
Let's group them together into a submenu.
Bin Meng [Thu, 13 May 2021 08:46:17 +0000 (16:46 +0800)]
riscv: Fix memmove and optimise memcpy when misalign
At present U-Boot SPL fails to boot on SiFive Unleashed board, due
to a load address misaligned exception happens when loading the FIT
image in spl_load_simple_fit(). The exception happens in memmove()
which is called by fdt_splice_().
Commit 8f0dc4cfd106 introduces an assembly version of memmove but
it does take misalignment into account (it checks if length is a
multiple of machine word size but pointers need also be aligned).
As a result it will generate misaligned load/store for the majority
of cases and causes significant performance regression on hardware
that traps misaligned load/store and emulate them using firmware.
The current behaviour of memcpy is that it checks if both src and
dest pointers are co-aligned (aka congruent modular SZ_REG). If
aligned, it will copy data word-by-word after first aligning
pointers to word boundary. If src and dst are not co-aligned,
however, byte-wise copy will be performed.
This patch was taken from the Linux kernel patch [1], which has not
been applied at the time being. It fixes the memmove and optimises
memcpy for misaligned cases. It will first align destination pointer
to word-boundary regardless whether src and dest are co-aligned or
not. If they indeed are, then wordwise copy is performed. If they
are not co-aligned, then it will load two adjacent words from src
and use shifts to assemble a full machine word. Some additional
assembly level micro-optimisation is also performed to ensure more
instructions can be compressed (e.g. prefer a0 to t6).
With this patch, U-Boot boots again on SiFive Unleashed board.
Sean Anderson [Sat, 15 May 2021 02:36:16 +0000 (22:36 -0400)]
riscv: Fix arch_fixup_fdt always failing without /chosen
If /chosen was missing, chosen_offset would never get updated with the new
/chosen node. This would cause fdt_setprop_u32 to fail. This patch fixes
this by setting chosen_offset. In addition, log any errors from setting
boot-hartid as well.
Fixes: 5370478d1c7 ("riscv: Add boot hartid to device tree") Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Rick Chen <rick@andestech.com> Reviewed-by: Atish Patra <atish.patra@wdc.com>
Bin Meng [Tue, 11 May 2021 12:04:12 +0000 (20:04 +0800)]
riscv: Split SiFive CLINT support between SPL and U-Boot proper
At present there is only one Kconfig option CONFIG_SIFIVE_CLINT to
control the enabling of SiFive CLINT support in both SPL (M-mode)
and U-Boot proper (S-mode). So for a typical SPL config that the
SiFive CLINT driver is enabled in both SPL and U-Boot proper, that
means the S-mode U-Boot tries to access the memory-mapped CLINT
registers directly, instead of the normal 'rdtime' instruction.
This was not a problem before, as the hardware does not forbid the
access from S-mode. However this becomes an issue now with OpenSBI
commit 8b569803475e ("lib: utils/sys: Add CLINT memregion in the root domain")
that the SiFive CLINT register space is protected by PMP for M-mode
access only. U-Boot proper does not boot any more with the latest
OpenSBI, that access exceptions are fired forever from U-Boot when
trying to read the timer value via the SiFive CLINT driver in U-Boot.
To solve this, we need to split current SiFive CLINT support between
SPL and U-Boot proper, using 2 separate Kconfig options.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Sean Anderson <seanga2@gmail.com>
Andre Przywara [Wed, 5 May 2021 12:51:03 +0000 (13:51 +0100)]
usb: musb-new: Extend and move Allwinner quirk into Kconfig
All newer Allwinner SoCs (since about 2013) miss the CONFIGDATA register
in their MUSB implementation, so they need a quirk to hardcode this.
Currently this quirk depends on listing the SoCs affected in musb_reg.h,
which means that this list needs to grow with every new chip.
Move the quirk feature into Kconfig, next to PIO_ONLY, and change the
default to y (for Allwinner builds), while listing the early
implementations as exceptions.
This fixes USB peripheral operation on some newer SoCs, which were not
explicitly listed before.
Tested on H6, H616, R40 (which were broken before), and also on the H5
and A20, for regressions.
Signed-off-by: Andre Przywara <andre.przywara@arm.com>
This patch adds the base support for the Marvell Octeon TX2 CN913x DB.
Only one defconfig is added with this patch. Other board variants are
available (NAND, MMC booting) and images for these boards can be
generated by following the documentation added in the included README.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
arm: octeontx2: Add dtsi/dts files for Octeon TX2 CN913x DB
This patch adds the dtsi/dts files needed to support the Marvell
Octeon TX2 CN913x DB. This is only the base port with not all
interfaces supported fully.
Signed-off-by: Konstantin Porotchkin <kostap@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
Stefan Roese [Wed, 5 May 2021 07:15:10 +0000 (09:15 +0200)]
cmd: mvebu: Rename rx_training to mvebu_comphy_rx_training
Rename the misleading cmd "rx_training" to "mvebu_comphy_rx_training" to
avoid confusion and mixup with DDR3/4 training. This makes it clear,
that this command is platform specific and handles the COMPHY RX
training.
Also depend this cmd on ARMADA_8K and not TARGET_MVEBU_ARMADA_8K to make
is available for OcteonTX2 CN913x.
Signed-off-by: Stefan Roese <sr@denx.de> Cc: Pali Rohár <pali@kernel.org> Cc: Marek Behun <marek.behun@nic.cz> Cc: Kostya Porotchkin <kostap@marvell.com> Cc: Nadav Haklai <nadavh@marvell.com> Acked-by: Marek Behún <marek.behun@nic.cz> Acked-by: Pali Rohár <pali@kernel.org>
Marcin Wojtas [Fri, 30 Apr 2021 13:33:15 +0000 (15:33 +0200)]
pcie: designware: mvebu: do not configure ATU for IO when not used
The pcie_dw_mvebu configure ATU regions for memory, configuration
and IO space types. However the latter is not obligatory
and when not specified in the device tree, causes wrong
ATU configuration. Fix that by adding a dependency on the
detected PCIE regions count.
arm64: mvebu: do not map firmware RT service region
There is region left by ATF, which needs to remain in memory to provide RT
services. To prevent overwriting it by u-boot, do not provide any mapping
for this memory region, so any attempt to access it will trigger
synchronous exception.
Update sr 2021-04-12:
Don't update armada3700/cpu.c mmu table, as this has specific changes
included in mainline.
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Signed-off-by: Stefan Roese <sr@denx.de>
After commit 1fe929ed497bcc8975be8d37383ebafd22b99dd2
("spi: kirkwood: prevent configuring speed exceeding max controller freq")
the spi frequency could be set to 0 on platform where spi-max-frequency
is not defined (e.g. on armada-388-gp). Prevent limiting speed in
mentioned cases.
Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Tested-by: Kostya Porotchkin <kostap@marvell.com> Reviewed-by: Marcin Wojtas <marcin@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
Ken Ma [Fri, 30 Apr 2021 13:26:29 +0000 (15:26 +0200)]
spi: kirkwood: support extended baud rates
The Armada SoC family implementation of this SPI hardware module has
extended the configuration register to allow for a wider range of SPI
clock rates. Specifically the Serial Baud Rate Pre-selection bits in the
SPI Interface Configuration Register now also use bits 6 and 7 as well.
Modify the baud rate calculation to handle these differences for the
Armada case. Potentially a baud rate can be setup using a number of
different pre-scalar and scalar combinations. This code tries all
possible pre-scalar divisors (8 in total) to try and find the most
accurate set.
Signed-off-by: Ken Ma <make@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
Neil Armstrong [Wed, 5 May 2021 07:52:08 +0000 (09:52 +0200)]
net: dwmac_meson8b: do not set TX delay in TXID & RXID
When the PHY interface is set as TXID & RXID, the delays should be taken from DT,
but first they should not be hardcoded since the PHY driver will set them.
Fixes: 798424e857 ("net: designware: add Amlogic Meson8b & later glue driver") Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
Vincent Chen [Mon, 3 May 2021 07:26:49 +0000 (15:26 +0800)]
pwm: sifive: make set_config() and set_enable() work properly
The pwm_sifive_set_config() and pwm_sifive_set_enable() cannot work
properly due to the wrong implementations. It will cause the u-boot
PWM command to not work as expected. The bugs will be resolved in this
patch.
Signed-off-by: Vincent Chen <vincent.chen@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
Sean Anderson [Fri, 9 Apr 2021 02:13:08 +0000 (22:13 -0400)]
clk: Add support for the k210 clock driver pre-relocation
Variables which had previously been stored in .bss are moved to .data. In
addition, probed needs to be reset when the clock driver is re-bound
post-relocation.
Sean Anderson [Fri, 9 Apr 2021 02:13:05 +0000 (22:13 -0400)]
clk: k210: Fix PLL enable always getting taken
This conditional always evaluated as false, regardless of the value of reg.
Fix it so that it properly tests the bits in the PLL register. Also test
PLL_EN, now that we set it.
Reported-by: Damien Le Moal <Damien.LeMoal@wdc.com> Signed-off-by: Sean Anderson <seanga2@gmail.com>
Sean Anderson [Fri, 9 Apr 2021 02:13:03 +0000 (22:13 -0400)]
clk: Warn on failure to assign rate
If the user/dev explicitly requests a clock be assigned a certain rate,
then we should warn them if we can't do it. This makes it clear if the
clock is running at the default rate.
Kory Maincent [Tue, 4 May 2021 17:31:27 +0000 (19:31 +0200)]
arm: sunxi: add support for DIP detection to CHIP board
Add the extension_board_scan specific function to scan the information
of the EEPROM on one-wire and fill the extension struct.
Add the Kconfig symbol to enable the needs to detect DIPs.
Signed-off-by: Kory Maincent <kory.maincent@bootlin.com> Reviewed-by: Maxime Ripard <maxime@cerno.tech> Acked-by: Andre Przywara <andre.przywara@arm.com>
Kory Maincent [Tue, 4 May 2021 17:31:26 +0000 (19:31 +0200)]
w1: replace dt detection by automatic detection
This patch changes the functioning of the detection of w1 devices.
The old way was a comparison between detected w1 and the ones described in
the device tree. Now it will just look for the driver matching the family
id of the w1 detected.
The patch is inspired from Maxime Ripard code.
Signed-off-by: Kory Maincent <kory.maincent@bootlin.com> Reviewed-by: Maxime Ripard <maxime@cerno.tech>
Kory Maincent [Tue, 4 May 2021 17:31:24 +0000 (19:31 +0200)]
ti/common: add support for extension_scan_board function
The BeagleBone platforms all use a common mechanism to discover and
identify extension boards (called "capes"): each extension board has an
I2C-connected EEPROM describing itself.
This patch implements a generic extension_scan_board() feature that can
be used by all BeagleBone platforms to read those I2C EEPROMs and fill
in the list of "extension" structures.
Following commits will enable this common logic on two BeagleBone
platforms.
Kory Maincent [Tue, 4 May 2021 17:31:23 +0000 (19:31 +0200)]
pytest: add sandbox test for "extension" command
This commit extends the sandbox to implement a dummy
extension_board_scan() function and enables the extension command in
the sandbox configuration. It then adds a test that checks the proper
functionality of the extension command by applying two Device Tree
overlays to the sandbox Device Tree.
Signed-off-by: Kory Maincent <kory.maincent@bootlin.com>
[trini: Limit to running on sandbox] Signed-off-by: Tom Rini <trini@konsulko.com>
Kory Maincent [Tue, 4 May 2021 17:31:22 +0000 (19:31 +0200)]
cmd: add support for a new "extension" command
This patch adds a new "extension" command, which aims at detecting
extension boards connected to the hardware platform, and apply the
Device Tree overlays that describe the hardware present on those
extension boards.
In order to enable this mechanism, board-specific code must implement
the extension_board_scan() function that fills in a linked list of
"struct extension", each describing one extension board. In addition,
the board-specific code must select the SUPPORT_EXTENSION_SCAN Kconfig
boolean.
Based on this:
- "extension scan" makes the generic code call the board-specific
extension_board_scan() function to retrieve the list of detected
extension boards.
- "extension list" allows to list the detected extension boards.
- "extension apply <number>|all" allows to apply the Device Tree
overlay(s) corresponding to one, or all, extension boards
The latter requires two environment variables to exist and set one variable
to run:
- extension_overlay_addr: the RAM address where to load the Device
Tree overlays
- extension_overlay_cmd: the U-Boot command to load one overlay.
Indeed, the location and mechanism to load DT overlays is very setup
specific.
- extension_overlay_name: set by the command: the name of the DT which
will be load during the execution.
When calling the command described in the extension_overlay_cmd
variable, the variable extension_overlay_name will be defined. So a
typical extension_overlay_cmd will look like this:
Here is an example on how to use it:
=> run loadfdt
=> fdt addr $fdtaddr
=> setenv extension_overlay_addr 0x1000
=> setenv extension_overlay_cmd 'load mmc 0:1 ${extension_overlay_addr} /boot/${extension_overlay_name}'
=> extension scan
Found 1 extension board(s).
=> extension apply 0
519 bytes read in 3 ms (168.9 KiB/s)
Signed-off-by: Kory Maincent <kory.maincent@bootlin.com> Reviewed-by: Maxime Ripard <maxime@cerno.tech>
Marek Vasut [Sat, 3 Apr 2021 14:58:49 +0000 (16:58 +0200)]
ARM: renesas: Scrub duplicate memory nodes from DT on Gen3
Scrub duplicate /memory@* node entries here. Some R-Car DTs might
contain multiple /memory@* nodes, however fdt_fixup_memory_banks()
either generates single /memory node or updates the first /memory
node. Any remaining memory nodes are thus potential duplicates.
However, it is not possible to delete all the memory nodes right
away, since some of those might not be DRAM memory nodes, but some
sort of other memory. Thus, delete only the memory nodes which are
in the R-Car3 DBSC ranges.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Marek Vasut [Wed, 12 May 2021 19:34:11 +0000 (21:34 +0200)]
ARM: rmobile: Add missing rcar-common/common.c to Beacon RZG2M kit
The rcar-common/common.c contains various common board functions shared
by all R-Car and RZG boards. This board is not compiling the file in, so
add it. This way, part of the board code can be de-duplicated too.
Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Adam Ford <aford173@gmail.com>
net: ti: am65-cpsw-nuss: Prepare to support non primary ext port
CPSW NUSS IP on K3 SoCs can have more than one external port (upto 8)
Therefore increase AM65_CPSW_CPSWNU_MAX_PORTS to 9 (8 ext + 1 Root port)
as preparation to allow any one of the 8 ports to be used as ethernet
interface in U-Boot.
projects / u-boot.git / log