From: Jonas Karlman <jonas@kwiboo.se>
Date: Mon, 31 Jul 2023 04:28:34 +0000 (+0000)
Subject: rockchip: rk3568-rock-3a: Fix pcie2x1 and pcie3x2 pinctrl override
X-Git-Url: http://git.dujemihanovic.xyz/login.html?a=commitdiff_plain;h=def50c66ccc839da8df8e31a4e3a7decaaaa2b17;p=u-boot.git

rockchip: rk3568-rock-3a: Fix pcie2x1 and pcie3x2 pinctrl override

The pcie pinctrl override added in the commit a76aa6ffa6cd ("rockchip:
rk3568-rock-3a: Enable PCIe and NVMe support") is causing a pinmux issue
on linux when using a EFI boot flow.

The pcie reset-gpios must however be configured with gpio function, or
the device will freeze running pci enum and nothing is connected.

Adjust the pinctrl override in u-boot.dtsi to fix this issue. PCIe/NVMe
continues to work in both U-Boot and linux after this change.

Also revert disable of sdmmc2 and uart1 to fix use of wifi in linux when
using a EFI boot flow.

Fixes: a76aa6ffa6cd ("rockchip: rk3568-rock-3a: Enable PCIe and NVMe support")
Fixes: 073d911ae64a ("rockchip: rk3568-rock-3a: Sync device tree from linux")
Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
---

diff --git a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
index a36a329f59..b05b7151e6 100644
--- a/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
+++ b/arch/arm/dts/rk3568-rock-3a-u-boot.dtsi
@@ -12,12 +12,8 @@
 	};
 };
 
-&pcie2x1 {
-	pinctrl-0 = <&pcie20m1_pins &pcie_reset_h>;
-};
-
 &pcie3x2 {
-	pinctrl-0 = <&pcie30x2m1_pins &pcie3x2_reset_h>;
+	pinctrl-0 = <&pcie3x2_reset_h>;
 };
 
 &pinctrl {
@@ -53,14 +49,6 @@
 	};
 };
 
-&sdmmc2 {
-	status = "disabled";
-};
-
-&uart1 {
-	status = "disabled";
-};
-
 &uart2 {
 	clock-frequency = <24000000>;
 	bootph-all;