From: Rick Chen <rick@andestech.com>
Date: Tue, 2 Apr 2019 07:56:42 +0000 (+0800)
Subject: riscv: ax25: Andes specific cache shall only support in M-mode
X-Git-Url: http://git.dujemihanovic.xyz/login.html?a=commitdiff_plain;h=dda00ae4ef357233a72c74e6c02d27b70c844422;p=u-boot.git

riscv: ax25: Andes specific cache shall only support in M-mode

Limit the cache configuration only can be supported in M mode.
It can not be manipulated in S mode.

Signed-off-by: Rick Chen <rick@andestech.com>
Cc: Greentime Hu <greentime@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de>
---

diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig
index 68bd4e9419..6b4b92e692 100644
--- a/arch/riscv/cpu/ax25/Kconfig
+++ b/arch/riscv/cpu/ax25/Kconfig
@@ -14,6 +14,7 @@ if RISCV_NDS
 
 config RISCV_NDS_CACHE
 	bool "AndeStar V5 families specific cache support"
+	depends on RISCV_MMODE
 	help
 	  Provide Andes Technology AndeStar V5 families specific cache support.