From: Leo Yu-Chi Liang <ycliang@andestech.com>
Date: Tue, 28 May 2024 12:49:57 +0000 (+0800)
Subject: riscv: remove cache enablement in start.S
X-Git-Url: http://git.dujemihanovic.xyz/login.html?a=commitdiff_plain;h=cea0ed2e3f37a36e6243bed8c3491d2281c30287;p=u-boot.git

riscv: remove cache enablement in start.S

Cache could be enabled in harts_early_init board-specific hook,
so remove cache enablement in start.S

Signed-off-by: Leo Yu-Chi Liang <ycliang@andestech.com>
---

diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index a9e1935692..8e58f641f1 100644
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -210,10 +210,6 @@ wait_for_gd_init:
 	bnez	s2, secondary_hart_loop
 #endif
 
-	/* Enable cache */
-	jal	icache_enable
-	jal	dcache_enable
-
 #ifdef CONFIG_DEBUG_UART
 	jal	debug_uart_init
 #endif