From: Marek Vasut Date: Mon, 20 May 2019 01:27:27 +0000 (+0200) Subject: sh: ap325rxa: Remove the board X-Git-Url: http://git.dujemihanovic.xyz/login.html?a=commitdiff_plain;h=c81b1a8a71fd9a807cbf9aef17f84bec6969a269;p=u-boot.git sh: ap325rxa: Remove the board Last change to this board was done in 2016, has no prospects of ever being converted to DM, drop it. Signed-off-by: Marek Vasut Cc: Chris Brandt Cc: Nobuhiro Iwamatsu Cc: Vladimir Zapolskiy Cc: Yoshihiro Shimoda --- diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig index 036f54a4df..da4bfd2cc3 100644 --- a/arch/sh/Kconfig +++ b/arch/sh/Kconfig @@ -21,10 +21,6 @@ choice prompt "Target select" optional -config TARGET_AP325RXA - bool "Renesas AP-325RXA" - select CPU_SH4 - config TARGET_MIGOR bool "Migo-R" select CPU_SH4 @@ -68,7 +64,6 @@ config SYS_CPU source "arch/sh/lib/Kconfig" source "board/renesas/MigoR/Kconfig" -source "board/renesas/ap325rxa/Kconfig" source "board/renesas/r0p7734/Kconfig" source "board/renesas/r2dplus/Kconfig" source "board/renesas/r7780mp/Kconfig" diff --git a/board/renesas/ap325rxa/Kconfig b/board/renesas/ap325rxa/Kconfig deleted file mode 100644 index c8f2de2959..0000000000 --- a/board/renesas/ap325rxa/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_AP325RXA - -config SYS_BOARD - default "ap325rxa" - -config SYS_VENDOR - default "renesas" - -config SYS_CONFIG_NAME - default "ap325rxa" - -endif diff --git a/board/renesas/ap325rxa/MAINTAINERS b/board/renesas/ap325rxa/MAINTAINERS deleted file mode 100644 index bdc49c5ec9..0000000000 --- a/board/renesas/ap325rxa/MAINTAINERS +++ /dev/null @@ -1,7 +0,0 @@ -AP325RXA BOARD -M: Nobuhiro Iwamatsu -M: Nobuhiro Iwamatsu -S: Maintained -F: board/renesas/ap325rxa/ -F: include/configs/ap325rxa.h -F: configs/ap325rxa_defconfig diff --git a/board/renesas/ap325rxa/Makefile b/board/renesas/ap325rxa/Makefile deleted file mode 100644 index 6551b940d3..0000000000 --- a/board/renesas/ap325rxa/Makefile +++ /dev/null @@ -1,10 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0+ -######################################################################### Copyright (C) 2008 Renesas Solutions Corp. -# Copyright (C) 2008 Nobuhiro Iwamatsu -# -# board/ap325rxa/Makefile -# -# - -obj-y := ap325rxa.o cpld-ap325rxa.o -extra-y += lowlevel_init.o diff --git a/board/renesas/ap325rxa/ap325rxa.c b/board/renesas/ap325rxa/ap325rxa.c deleted file mode 100644 index 700a48687d..0000000000 --- a/board/renesas/ap325rxa/ap325rxa.c +++ /dev/null @@ -1,148 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * Copyright (C) 2008 Renesas Solutions Corp. - * Copyright (C) 2008 Nobuhiro Iwamatsu - */ - -#include -#include -#include -#include - -/* PRI control register */ -#define PRPRICR5 0xFF800048 /* LMB */ -#define PRPRICR5_D 0x2a - -/* FPGA control */ -#define FPGA_NAND_CTL 0xB410020C -#define FPGA_NAND_RST 0x0008 -#define FPGA_NAND_INIT 0x0000 -#define FPGA_NAND_RST_WAIT 10000 - -/* I/O port data */ -#define PACR_D 0x0000 -#define PBCR_D 0x0000 -#define PCCR_D 0x1000 -#define PDCR_D 0x0000 -#define PECR_D 0x0410 -#define PFCR_D 0xffff -#define PGCR_D 0x0000 -#define PHCR_D 0x5011 -#define PJCR_D 0x4400 -#define PKCR_D 0x7c00 -#define PLCR_D 0x0000 -#define PMCR_D 0x0000 -#define PNCR_D 0x0000 -#define PQCR_D 0x0000 -#define PRCR_D 0x0000 -#define PSCR_D 0x0000 -#define PTCR_D 0x0010 -#define PUCR_D 0x0fff -#define PVCR_D 0xffff -#define PWCR_D 0x0000 -#define PXCR_D 0x7500 -#define PYCR_D 0x0000 -#define PZCR_D 0x5540 - -/* Pin Function Controler data */ -#define PSELA_D 0x1410 -#define PSELB_D 0x0140 -#define PSELC_D 0x0000 -#define PSELD_D 0x0400 - -/* I/O Buffer Hi-Z data */ -#define HIZCRA_D 0x0000 -#define HIZCRB_D 0x1000 -#define HIZCRC_D 0x0000 -#define HIZCRD_D 0x0000 - -/* Module select reg data */ -#define MSELCRA_D 0x0014 -#define MSELCRB_D 0x0018 - -/* Module Stop reg Data */ -#define MSTPCR2_D 0xFFD9F280 - -/* CPLD loader */ -extern void init_cpld(void); - -int checkboard(void) -{ - puts("BOARD: AP325RXA\n"); - return 0; -} - -int board_init(void) -{ - /* Pin Function Controler Init */ - outw(PSELA_D, PSELA); - outw(PSELB_D, PSELB); - outw(PSELC_D, PSELC); - outw(PSELD_D, PSELD); - - /* I/O Buffer Hi-Z Init */ - outw(HIZCRA_D, HIZCRA); - outw(HIZCRB_D, HIZCRB); - outw(HIZCRC_D, HIZCRC); - outw(HIZCRD_D, HIZCRD); - - /* Module select reg Init */ - outw(MSELCRA_D, MSELCRA); - outw(MSELCRB_D, MSELCRB); - - /* Module Stop reg Init */ - outl(MSTPCR2_D, MSTPCR2); - - /* I/O ports */ - outw(PACR_D, PACR); - outw(PBCR_D, PBCR); - outw(PCCR_D, PCCR); - outw(PDCR_D, PDCR); - outw(PECR_D, PECR); - outw(PFCR_D, PFCR); - outw(PGCR_D, PGCR); - outw(PHCR_D, PHCR); - outw(PJCR_D, PJCR); - outw(PKCR_D, PKCR); - outw(PLCR_D, PLCR); - outw(PMCR_D, PMCR); - outw(PNCR_D, PNCR); - outw(PQCR_D, PQCR); - outw(PRCR_D, PRCR); - outw(PSCR_D, PSCR); - outw(PTCR_D, PTCR); - outw(PUCR_D, PUCR); - outw(PVCR_D, PVCR); - outw(PWCR_D, PWCR); - outw(PXCR_D, PXCR); - outw(PYCR_D, PYCR); - outw(PZCR_D, PZCR); - - /* PRI control register Init */ - outl(PRPRICR5_D, PRPRICR5); - - /* cpld init */ - init_cpld(); - - return 0; -} - -void led_set_state(unsigned short value) -{ -} - -void ide_set_reset(int idereset) -{ - outw(FPGA_NAND_RST, FPGA_NAND_CTL); /* NAND RESET */ - udelay(FPGA_NAND_RST_WAIT); - outw(FPGA_NAND_INIT, FPGA_NAND_CTL); -} - -int board_eth_init(bd_t *bis) -{ - int rc = 0; -#ifdef CONFIG_SMC911X - rc = smc911x_initialize(0, CONFIG_SMC911X_BASE); -#endif - return rc; -} diff --git a/board/renesas/ap325rxa/cpld-ap325rxa.c b/board/renesas/ap325rxa/cpld-ap325rxa.c deleted file mode 100644 index 5d9dc9387e..0000000000 --- a/board/renesas/ap325rxa/cpld-ap325rxa.c +++ /dev/null @@ -1,204 +0,0 @@ -/*************************************************************** - * Project: - * CPLD SlaveSerial Configuration via embedded microprocessor. - * - * Copyright info: - * - * This is free software; you can redistribute it and/or modify - * it as you like. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. - * - * Description: - * - * This is the main source file that will allow a microprocessor - * to configure Xilinx Virtex, Virtex-E, Virtex-EM, Virtex-II, - * and Spartan-II devices via the SlaveSerial Configuration Mode. - * This code is discussed in Xilinx Application Note, XAPP502. - * - * History: - * 3-October-2001 MN/MP - Created - * 20-August-2008 Renesas Solutions - Modified to SH7723 - ****************************************************************/ - -#include - -/* Serial */ -#define SCIF_BASE 0xffe00000 /* SCIF0 */ -#define SCSMR (vu_short *)(SCIF_BASE + 0x00) -#define SCBRR (vu_char *)(SCIF_BASE + 0x04) -#define SCSCR (vu_short *)(SCIF_BASE + 0x08) -#define SC_TDR (vu_char *)(SCIF_BASE + 0x0C) -#define SC_SR (vu_short *)(SCIF_BASE + 0x10) -#define SCFCR (vu_short *)(SCIF_BASE + 0x18) -#define RFCR (vu_long *)0xFE400020 - -#define SCSCR_INIT 0x0038 -#define SCSCR_CLR 0x0000 -#define SCFCR_INIT 0x0006 -#define SCSMR_INIT 0x0080 -#define RFCR_CLR 0xA400 -#define SCI_TD_E 0x0020 -#define SCI_TDRE_CLEAR 0x00df - -#define BPS_SETTING_VALUE 1 /* 12.5MHz */ -#define WAIT_RFCR_COUNTER 500 - -/* CPLD data size */ -#define CPLD_DATA_SIZE 169216 - -/* out */ -#define CPLD_PFC_ADR ((vu_short *)0xA4050112) - -#define CPLD_PROG_ADR ((vu_char *)0xA4050132) -#define CPLD_PROG_DAT 0x80 - -/* in */ -#define CPLD_INIT_ADR ((vu_char *)0xA4050132) -#define CPLD_INIT_DAT 0x40 -#define CPLD_DONE_ADR ((vu_char *)0xA4050132) -#define CPLD_DONE_DAT 0x20 - -/* data */ -#define CPLD_NOMAL_START 0xA0A80000 -#define CPLD_SAFE_START 0xA0AC0000 -#define MODE_SW (vu_char *)0xA405012A - -static void init_cpld_loader(void) -{ - - *SCSCR = SCSCR_CLR; - *SCFCR = SCFCR_INIT; - *SCSMR = SCSMR_INIT; - - *SCBRR = BPS_SETTING_VALUE; - - *RFCR = RFCR_CLR; /* Refresh counter clear */ - - while (*RFCR < WAIT_RFCR_COUNTER) - ; - - *SCFCR = 0x0; /* RTRG=00, TTRG=00 */ - /* MCE=0,TFRST=0,RFRST=0,LOOP=0 */ - *SCSCR = SCSCR_INIT; -} - -static int check_write_ready(void) -{ - u16 status = *SC_SR; - return status & SCI_TD_E; -} - -static void write_cpld_data(char ch) -{ - while (!check_write_ready()) - ; - - *SC_TDR = ch; - *SC_SR; - *SC_SR = SCI_TDRE_CLEAR; -} - -static int delay(void) -{ - int i; - int c = 0; - for (i = 0; i < 200; i++) { - c = *(volatile int *)0xa0000000; - } - return c; -} - -/*********************************************************************** - * - * Function: slave_serial - * - * Description: Initiates SlaveSerial Configuration. - * Calls ShiftDataOut() to output serial data - * - ***********************************************************************/ -static void slave_serial(void) -{ - int i; - unsigned char *flash; - - *CPLD_PROG_ADR |= CPLD_PROG_DAT; /* PROGRAM_OE HIGH */ - delay(); - - /* - * Toggle Program Pin by Toggling Program_OE bit - * This is accomplished by writing to the Program Register in the CPLD - * - * NOTE: The Program_OE bit should be driven high to bring the Virtex - * Program Pin low. Likewise, it should be driven low - * to bring the Virtex Program Pin to High-Z - */ - - *CPLD_PROG_ADR &= ~CPLD_PROG_DAT; /* PROGRAM_OE LOW */ - delay(); - - /* - * Bring Program High-Z - * (Drive Program_OE bit low to bring Virtex Program Pin to High-Z - */ - - /* Program_OE bit Low brings the Virtex Program Pin to High Z: */ - *CPLD_PROG_ADR |= CPLD_PROG_DAT; /* PROGRAM_OE HIGH */ - - while ((*CPLD_INIT_ADR & CPLD_INIT_DAT) == 0) - delay(); - - /* Begin Slave-Serial Configuration */ - flash = (unsigned char *)CPLD_NOMAL_START; - - for (i = 0; i < CPLD_DATA_SIZE; i++) - write_cpld_data(*flash++); -} - -/*********************************************************************** - * - * Function: check_done_bit - * - * Description: This function takes monitors the CPLD Input Register - * by checking the status of the DONE bit in that Register. - * By doing so, it monitors the Xilinx Virtex device's DONE - * Pin to see if configuration bitstream has been properly - * loaded - * - ***********************************************************************/ -static void check_done_bit(void) -{ - while (!(*CPLD_DONE_ADR & CPLD_DONE_DAT)) - ; -} - -/*********************************************************************** - * - * Function: init_cpld - * - * Description: Begins Slave Serial configuration of Xilinx FPGA - * - ***********************************************************************/ -void init_cpld(void) -{ - /* Init serial device */ - init_cpld_loader(); - - if (*CPLD_DONE_ADR & CPLD_DONE_DAT) /* Already DONE */ - return; - - *((vu_short *)HIZCRB) = 0x0000; - *CPLD_PFC_ADR = 0x7c00; /* FPGA PROG = OUTPUT */ - - /* write CPLD data from NOR flash to device */ - slave_serial(); - - /* - * Monitor the DONE bit in the CPLD Input Register to see if - * configuration successful - */ - - check_done_bit(); -} diff --git a/board/renesas/ap325rxa/lowlevel_init.S b/board/renesas/ap325rxa/lowlevel_init.S deleted file mode 100644 index 1a24581c32..0000000000 --- a/board/renesas/ap325rxa/lowlevel_init.S +++ /dev/null @@ -1,170 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2008 Renesas Solutions Corp. - * Copyright (C) 2008 Nobuhiro Iwamatsu - * - * board/ap325rxa/lowlevel_init.S - */ - -#include -#include -#include - -/* - * Board specific low level init code, called _very_ early in the - * startup sequence. Relocation to SDRAM has not happened yet, no - * stack is available, bss section has not been initialised, etc. - * - * (Note: As no stack is available, no subroutines can be called...). - */ - - .global lowlevel_init - - .text - .align 2 - -lowlevel_init: - write16 DRVCRA_A, DRVCRA_D - - write16 DRVCRB_A, DRVCRB_D - - write16 RWTCSR_A, RWTCSR_D1 - - write16 RWTCNT_A, RWTCNT_D - - write16 RWTCSR_A, RWTCSR_D2 - - write32 FRQCR_A, FRQCR_D - - write32 CMNCR_A, CMNCR_D - - write32 CS0BCR_A, CS0BCR_D - - write32 CS4BCR_A, CS4BCR_D - - write32 CS5ABCR_A, CS5ABCR_D - - write32 CS5BBCR_A, CS5BBCR_D - - write32 CS6ABCR_A, CS6ABCR_D - - write32 CS6BBCR_A, CS6BBCR_D - - write32 CS0WCR_A, CS0WCR_D - - write32 CS4WCR_A, CS4WCR_D - - write32 CS5AWCR_A, CS5AWCR_D - - write32 CS5BWCR_A, CS5BWCR_D - - write32 CS6AWCR_A, CS6AWCR_D - - write32 CS6BWCR_A, CS6BWCR_D - - write32 SBSC_SDCR_A, SBSC_SDCR_D1 - - write32 SBSC_SDWCR_A, SBSC_SDWCR_D - - write32 SBSC_SDPCR_A, SBSC_SDPCR_D - - write32 SBSC_RTCSR_A, SBSC_RTCSR_D - - write32 SBSC_RTCNT_A, SBSC_RTCNT_D - - write32 SBSC_RTCOR_A, SBSC_RTCOR_D - - write8 SBSC_SDMR3_A1, SBSC_SDMR3_D - - write8 SBSC_SDMR3_A2, SBSC_SDMR3_D - - mov.l SLEEP_CNT, r1 -2: tst r1, r1 - nop - bf/s 2b - dt r1 - - write8 SBSC_SDMR3_A3, SBSC_SDMR3_D - - write32 SBSC_SDCR_A, SBSC_SDCR_D2 - - write32 CCR_A, CCR_D - - ! BL bit off (init = ON) (?!?) - - stc sr, r0 ! BL bit off(init=ON) - mov.l SR_MASK_D, r1 - and r1, r0 - ldc r0, sr - - rts - mov #0, r0 - - .align 2 - -DRVCRA_A: .long DRVCRA -DRVCRB_A: .long DRVCRB -DRVCRA_D: .word 0x4555 -DRVCRB_D: .word 0x0005 - -RWTCSR_A: .long RWTCSR -RWTCNT_A: .long RWTCNT -FRQCR_A: .long FRQCR -RWTCSR_D1: .word 0xa507 -RWTCSR_D2: .word 0xa504 -RWTCNT_D: .word 0x5a00 -.align 2 -FRQCR_D: .long 0x0b04474a - -SBSC_SDCR_A: .long SBSC_SDCR -SBSC_SDWCR_A: .long SBSC_SDWCR -SBSC_SDPCR_A: .long SBSC_SDPCR -SBSC_RTCSR_A: .long SBSC_RTCSR -SBSC_RTCNT_A: .long SBSC_RTCNT -SBSC_RTCOR_A: .long SBSC_RTCOR -SBSC_SDMR3_A1: .long 0xfe510000 -SBSC_SDMR3_A2: .long 0xfe500242 -SBSC_SDMR3_A3: .long 0xfe5c0042 - -SBSC_SDCR_D1: .long 0x92810112 -SBSC_SDCR_D2: .long 0x92810912 -SBSC_SDWCR_D: .long 0x05162482 -SBSC_SDPCR_D: .long 0x00300087 -SBSC_RTCSR_D: .long 0xa55a0212 -SBSC_RTCNT_D: .long 0xa55a0000 -SBSC_RTCOR_D: .long 0xa55a0040 -SBSC_SDMR3_D: .long 0x00 - -CMNCR_A: .long CMNCR -CS0BCR_A: .long CS0BCR -CS4BCR_A: .long CS4BCR -CS5ABCR_A: .long CS5ABCR -CS5BBCR_A: .long CS5BBCR -CS6ABCR_A: .long CS6ABCR -CS6BBCR_A: .long CS6BBCR -CS0WCR_A: .long CS0WCR -CS4WCR_A: .long CS4WCR -CS5AWCR_A: .long CS5AWCR -CS5BWCR_A: .long CS5BWCR -CS6AWCR_A: .long CS6AWCR -CS6BWCR_A: .long CS6BWCR - -CMNCR_D: .long 0x00000013 -CS0BCR_D: .long 0x24920400 -CS4BCR_D: .long 0x24920400 -CS5ABCR_D: .long 0x24920400 -CS5BBCR_D: .long 0x7fff0600 -CS6ABCR_D: .long 0x24920400 -CS6BBCR_D: .long 0x24920600 -CS0WCR_D: .long 0x00000480 -CS4WCR_D: .long 0x00000480 -CS5AWCR_D: .long 0x00000380 -CS5BWCR_D: .long 0x00000080 -CS6AWCR_D: .long 0x00000300 -CS6BWCR_D: .long 0x00000540 - -CCR_A: .long 0xff00001c -CCR_D: .long 0x0000090d - -SLEEP_CNT: .long 0x00000800 -SR_MASK_D: .long 0xEFFFFF0F diff --git a/configs/ap325rxa_defconfig b/configs/ap325rxa_defconfig deleted file mode 100644 index d2f0d7fc42..0000000000 --- a/configs/ap325rxa_defconfig +++ /dev/null @@ -1,37 +0,0 @@ -CONFIG_SH=y -CONFIG_SYS_TEXT_BASE=0x8FFC0000 -CONFIG_TARGET_AP325RXA=y -CONFIG_BOOTDELAY=3 -CONFIG_USE_BOOTARGS=y -CONFIG_BOOTARGS="console=ttySC2,38400" -CONFIG_VERSION_VARIABLE=y -# CONFIG_CMDLINE_EDITING is not set -# CONFIG_AUTO_COMPLETE is not set -# CONFIG_CMD_BDI is not set -# CONFIG_CMD_CONSOLE is not set -# CONFIG_CMD_BOOTD is not set -# CONFIG_CMD_RUN is not set -# CONFIG_CMD_IMI is not set -# CONFIG_CMD_XIMG is not set -# CONFIG_CMD_EDITENV is not set -# CONFIG_CMD_ENV_EXISTS is not set -CONFIG_CMD_IDE=y -CONFIG_CMD_SDRAM=y -# CONFIG_CMD_ECHO is not set -# CONFIG_CMD_ITEST is not set -# CONFIG_CMD_SOURCE is not set -# CONFIG_CMD_SETEXPR is not set -CONFIG_CMD_PING=y -# CONFIG_CMD_MISC is not set -CONFIG_CMD_EXT2=y -CONFIG_DOS_PARTITION=y -CONFIG_ENV_IS_IN_FLASH=y -CONFIG_MTD_NOR_FLASH=y -CONFIG_FLASH_CFI_DRIVER=y -CONFIG_SYS_FLASH_CFI=y -CONFIG_SMC911X=y -CONFIG_SMC911X_BASE=0xB6080000 -CONFIG_SMC911X_32_BIT=y -CONFIG_BAUDRATE=38400 -CONFIG_SCIF_CONSOLE=y -CONFIG_USE_PRIVATE_LIBGCC=y diff --git a/include/configs/ap325rxa.h b/include/configs/ap325rxa.h deleted file mode 100644 index 901ce4da61..0000000000 --- a/include/configs/ap325rxa.h +++ /dev/null @@ -1,114 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Configuation settings for the Renesas Solutions AP-325RXA board - * - * Copyright (C) 2008 Renesas Solutions Corp. - * Copyright (C) 2008 Nobuhiro Iwamatsu - */ - -#ifndef __AP325RXA_H -#define __AP325RXA_H - -#define CONFIG_CPU_SH7723 1 - -#define CONFIG_DISPLAY_BOARDINFO -#undef CONFIG_SHOW_BOOT_PROGRESS - -/* MEMORY */ -#define AP325RXA_SDRAM_BASE (0x88000000) -#define AP325RXA_FLASH_BASE_1 (0xA0000000) -#define AP325RXA_FLASH_BANK_SIZE (128 * 1024 * 1024) - -/* undef to save memory */ -/* Monitor Command Prompt */ -/* Buffer size for Console output */ -#define CONFIG_SYS_PBSIZE 256 -/* List of legal baudrate settings for this board */ -#define CONFIG_SYS_BAUDRATE_TABLE { 38400 } - -/* SCIF */ -#define CONFIG_SCIF_A 1 /* SH7723 has SCIF and SCIFA */ -#define CONFIG_CONS_SCIF5 1 - -/* Suppress display of console information at boot */ - -#define CONFIG_SYS_MEMTEST_START (AP325RXA_SDRAM_BASE) -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024)) - -/* Enable alternate, more extensive, memory test */ -/* Scratch address used by the alternate memory test */ -#undef CONFIG_SYS_MEMTEST_SCRATCH - -/* Enable temporary baudrate change while serial download */ -#undef CONFIG_SYS_LOADS_BAUD_CHANGE - -#define CONFIG_SYS_SDRAM_BASE (AP325RXA_SDRAM_BASE) -/* maybe more, but if so u-boot doesn't know about it... */ -#define CONFIG_SYS_SDRAM_SIZE (128 * 1024 * 1024) -/* default load address for scripts ?!? */ -#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024) - -/* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */ -#define CONFIG_SYS_MONITOR_BASE (AP325RXA_FLASH_BASE_1) -/* Monitor size */ -#define CONFIG_SYS_MONITOR_LEN (128 * 1024) -/* Size of DRAM reserved for malloc() use */ -#define CONFIG_SYS_MALLOC_LEN (256 * 1024) -#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) - -/* FLASH */ -#undef CONFIG_SYS_FLASH_QUIET_TEST -/* print 'E' for empty sector on flinfo */ -#define CONFIG_SYS_FLASH_EMPTY_INFO -/* Physical start address of Flash memory */ -#define CONFIG_SYS_FLASH_BASE (AP325RXA_FLASH_BASE_1) -/* Max number of sectors on each Flash chip */ -#define CONFIG_SYS_MAX_FLASH_SECT 512 - -/* - * IDE support - */ -#define CONFIG_IDE_RESET 1 -#define CONFIG_SYS_PIO_MODE 1 -#define CONFIG_SYS_IDE_MAXBUS 1 /* IDE bus */ -#define CONFIG_SYS_IDE_MAXDEVICE 1 -#define CONFIG_SYS_ATA_BASE_ADDR 0xB4180000 -#define CONFIG_SYS_ATA_STRIDE 2 /* 1bit shift */ -#define CONFIG_SYS_ATA_DATA_OFFSET 0x200 /* data reg offset */ -#define CONFIG_SYS_ATA_REG_OFFSET 0x200 /* reg offset */ -#define CONFIG_SYS_ATA_ALT_OFFSET 0x210 /* alternate register offset */ -#define CONFIG_IDE_SWAP_IO - -/* if you use all NOR Flash , you change dip-switch. Please see Manual. */ -#define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE + (0 * AP325RXA_FLASH_BANK_SIZE)} - -/* Timeout for Flash erase operations (in ms) */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000) -/* Timeout for Flash write operations (in ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000) -/* Timeout for Flash set sector lock bit operations (in ms) */ -#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000) -/* Timeout for Flash clear lock bit operations (in ms) */ -#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000) - -/* - * Use hardware flash sectors protection instead - * of U-Boot software protection - */ -#undef CONFIG_SYS_DIRECT_FLASH_TFTP - -/* ENV setting */ -#define CONFIG_ENV_OVERWRITE 1 -#define CONFIG_ENV_SECT_SIZE (128 * 1024) -#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) -/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */ -#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE) -#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) - -/* Board Clock */ -#define CONFIG_SYS_CLK_FREQ 33333333 -#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ - -#endif /* __AP325RXA_H */