From: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Date: Wed, 29 Jan 2020 11:08:29 +0000 (+0300)
Subject: CLK: HSDK: Check for PLL bypass firstly
X-Git-Url: http://git.dujemihanovic.xyz/login.html?a=commitdiff_plain;h=b8f3ce013700893a3ed4ae280a2aec0ab95af3de;p=u-boot.git

CLK: HSDK: Check for PLL bypass firstly

Pll bypass has priority over enable/disable.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
---

diff --git a/drivers/clk/clk-hsdk-cgu.c b/drivers/clk/clk-hsdk-cgu.c
index 56ef08c032..69e6b24b66 100644
--- a/drivers/clk/clk-hsdk-cgu.c
+++ b/drivers/clk/clk-hsdk-cgu.c
@@ -377,14 +377,14 @@ static ulong pll_get(struct clk *sclk)
 
 	pr_debug("current configurarion: %#x\n", val);
 
-	/* Check if PLL is disabled */
-	if (val & CGU_PLL_CTRL_PD)
-		return 0;
-
 	/* Check if PLL is bypassed */
 	if (val & CGU_PLL_CTRL_BYPASS)
 		return PARENT_RATE;
 
+	/* Check if PLL is disabled */
+	if (val & CGU_PLL_CTRL_PD)
+		return 0;
+
 	/* input divider = reg.idiv + 1 */
 	idiv = 1 + ((val & CGU_PLL_CTRL_IDIV_MASK) >> CGU_PLL_CTRL_IDIV_SHIFT);
 	/* fb divider = 2*(reg.fbdiv + 1) */