From: Thierry Reding <treding@nvidia.com>
Date: Fri, 15 Mar 2019 15:32:33 +0000 (+0100)
Subject: pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS
X-Git-Tag: v2025.01-rc5-pxa1908~3022^2~18
X-Git-Url: http://git.dujemihanovic.xyz/login.html?a=commitdiff_plain;h=aec4298ccb337106fd0115b91d846a022fdf301d;p=u-boot.git

pci: Scale MAX_PCI_REGIONS based on CONFIG_NR_DRAM_BANKS

If a platform defines CONFIG_NR_DRAM_BANKS, each DRAM bank will be added
as a PCI region. The number of MAX_PCI_REGIONS therefore needs to scale
with the number of DRAM banks, otherwise we will end up with too little
space in the hose->regions array to store all system memory regions.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Simon Glass <sjg@chromium.org>
---

diff --git a/include/pci.h b/include/pci.h
index 5fb212cab1..9668503f09 100644
--- a/include/pci.h
+++ b/include/pci.h
@@ -545,7 +545,11 @@ extern void pci_cfgfunc_do_nothing(struct pci_controller* hose, pci_dev_t dev,
 extern void pci_cfgfunc_config_device(struct pci_controller* hose, pci_dev_t dev,
 				      struct pci_config_table *);
 
-#define MAX_PCI_REGIONS		7
+#ifdef CONFIG_NR_DRAM_BANKS
+#define MAX_PCI_REGIONS (CONFIG_NR_DRAM_BANKS + 7)
+#else
+#define MAX_PCI_REGIONS 7
+#endif
 
 #define INDIRECT_TYPE_NO_PCIE_LINK	1