From: Nishanth Menon <nm@ti.com>
Date: Thu, 21 Apr 2016 19:34:24 +0000 (-0500)
Subject: ARM: OMAP5: Enable ABB configuration for MM voltage domain
X-Git-Url: http://git.dujemihanovic.xyz/login.html?a=commitdiff_plain;h=a818097a330e73795dc0e783fbb67c5ec86b657f;p=u-boot.git

ARM: OMAP5: Enable ABB configuration for MM voltage domain

Since we setup the voltage and frequency for the MM domain, we *must*
setup the ABB configuration needed for the domain as well. If we do not
do this, kernel configuring just the frequency using the default boot
loader configured voltage can fail on many corner lot units.

Reported-by: Richard Woodruff <r-woodruff2@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
---

diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c
index 8fe695b992..da57b385c9 100644
--- a/arch/arm/cpu/armv7/omap-common/clocks-common.c
+++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c
@@ -632,6 +632,15 @@ void scale_vcores(struct vcores_data const *vcores)
 	val = optimize_vcore_voltage(&vcores->mm);
 	do_scale_vcore(vcores->mm.addr, val, vcores->mm.pmic);
 
+	/* Configure MM ABB LDO after scale */
+	abb_setup(vcores->mm.efuse.reg,
+		  (*ctrl)->control_wkup_ldovbb_mm_voltage_ctrl,
+		  (*prcm)->prm_abbldo_mm_setup,
+		  (*prcm)->prm_abbldo_mm_ctrl,
+		  (*prcm)->prm_irqstatus_mpu,
+		  vcores->mm.abb_tx_done_mask,
+		  OMAP_ABB_FAST_OPP);
+
 	val = optimize_vcore_voltage(&vcores->gpu);
 	do_scale_vcore(vcores->gpu.addr, val, vcores->gpu.pmic);
 
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c b/arch/arm/cpu/armv7/omap5/hw_data.c
index a4b31e42e2..dfb1df6bce 100644
--- a/arch/arm/cpu/armv7/omap5/hw_data.c
+++ b/arch/arm/cpu/armv7/omap5/hw_data.c
@@ -361,6 +361,7 @@ struct vcores_data omap5430_volts_es2 = {
 	.mm.value = VDD_MM_ES2,
 	.mm.addr = SMPS_REG_ADDR_45_IVA,
 	.mm.pmic = &palmas,
+	.mm.abb_tx_done_mask = OMAP_ABB_MM_TXDONE_MASK,
 };
 
 struct vcores_data dra752_volts = {
diff --git a/arch/arm/cpu/armv7/omap5/prcm-regs.c b/arch/arm/cpu/armv7/omap5/prcm-regs.c
index c55c6af9e5..d126a32231 100644
--- a/arch/arm/cpu/armv7/omap5/prcm-regs.c
+++ b/arch/arm/cpu/armv7/omap5/prcm-regs.c
@@ -352,6 +352,7 @@ struct omap_sys_ctrl_regs const omap5_ctrl = {
 	.control_emif1_sdram_config_ext		= 0x4AE0C144,
 	.control_emif2_sdram_config_ext		= 0x4AE0C148,
 	.control_wkup_ldovbb_mpu_voltage_ctrl	= 0x4AE0C318,
+	.control_wkup_ldovbb_mm_voltage_ctrl	= 0x4AE0C314,
 	.control_padconf_wkup_base		= 0x4AE0C800,
 	.control_smart1nopmio_padconf_0		= 0x4AE0CDA0,
 	.control_smart1nopmio_padconf_1		= 0x4AE0CDA4,
@@ -722,6 +723,7 @@ struct prcm_regs const omap5_es2_prcm = {
 	.cm_l3init_usb_otg_ss1_clkctrl = 0x4a0096f0,
 
 	/* prm irqstatus regs */
+	.prm_irqstatus_mpu = 0x4ae06010,
 	.prm_irqstatus_mpu_2 = 0x4ae06014,
 
 	/* l4 wkup regs */
@@ -751,6 +753,8 @@ struct prcm_regs const omap5_es2_prcm = {
 
 	.prm_abbldo_mpu_setup = 0x4ae07cdc,
 	.prm_abbldo_mpu_ctrl = 0x4ae07ce0,
+	.prm_abbldo_mm_setup = 0x4ae07ce4,
+	.prm_abbldo_mm_ctrl = 0x4ae07ce8,
 
 	/* SCRM stuff, used by some boards */
 	.scrm_auxclk0 = 0x4ae0a310,
diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h
index 1eeb8d5f62..cfec5b063c 100644
--- a/arch/arm/include/asm/arch-omap5/omap.h
+++ b/arch/arm/include/asm/arch-omap5/omap.h
@@ -215,6 +215,7 @@ struct s32ktimer {
 
 /* ABB tranxdone mask */
 #define OMAP_ABB_MPU_TXDONE_MASK		(0x1 << 7)
+#define OMAP_ABB_MM_TXDONE_MASK			(0x1 << 31)
 
 /* ABB efuse masks */
 #define OMAP5_ABB_FUSE_VSET_MASK		(0x1F << 24)
diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h
index d3e8417528..14c07fab34 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -234,6 +234,7 @@ struct prcm_regs {
 	u32 cm_l3init_usb_otg_ss1_clkctrl;
 	u32 cm_l3init_usb_otg_ss2_clkctrl;
 
+	u32 prm_irqstatus_mpu;
 	u32 prm_irqstatus_mpu_2;
 
 	/* cm2.l4per */
@@ -321,6 +322,8 @@ struct prcm_regs {
 	u32 prm_vc_cfg_i2c_clk;
 	u32 prm_abbldo_mpu_setup;
 	u32 prm_abbldo_mpu_ctrl;
+	u32 prm_abbldo_mm_setup;
+	u32 prm_abbldo_mm_ctrl;
 
 	u32 cm_div_m4_dpll_core;
 	u32 cm_div_m5_dpll_core;
@@ -441,6 +444,7 @@ struct omap_sys_ctrl_regs {
 	u32 control_emif1_sdram_config_ext;
 	u32 control_emif2_sdram_config_ext;
 	u32 control_wkup_ldovbb_mpu_voltage_ctrl;
+	u32 control_wkup_ldovbb_mm_voltage_ctrl;
 	u32 control_smart1nopmio_padconf_0;
 	u32 control_smart1nopmio_padconf_1;
 	u32 control_padconf_mode;