From: Stefan Roese <sr@denx.de>
Date: Thu, 14 May 2020 09:59:06 +0000 (+0200)
Subject: mips: traps: Set WG bit in EBase register on Octeon
X-Git-Url: http://git.dujemihanovic.xyz/login.html?a=commitdiff_plain;h=a02bc1f99275a17e1d29886c8c69398e9313842d;p=u-boot.git

mips: traps: Set WG bit in EBase register on Octeon

WG (bit 11) needs to be set on Octeon to enable writing bits 63:30 of
the exception base register.

Signed-off-by: Stefan Roese <sr@denx.de>
---

diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index 7538e6b2e0..17381301ec 100644
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -366,6 +366,7 @@
  * Bits in the coprocessor 0 EBase register.
  */
 #define EBASE_CPUNUM		0x3ff
+#define EBASE_WG		(_ULCAST_(1) << 11)
 
 /*
  * Bits in the coprocessor 0 config register.
diff --git a/arch/mips/lib/traps.c b/arch/mips/lib/traps.c
index b1ae02fcab..6ff9d20bd6 100644
--- a/arch/mips/lib/traps.c
+++ b/arch/mips/lib/traps.c
@@ -108,6 +108,10 @@ void trap_init(ulong reloc_addr)
 
 	saved_ebase = read_c0_ebase() & 0xfffff000;
 
+	/* Set WG bit on Octeon to enable writing to bits 63:30 */
+	if (IS_ENABLED(CONFIG_ARCH_OCTEON))
+		ebase |= EBASE_WG;
+
 	write_c0_ebase(ebase);
 	clear_c0_status(ST0_BEV);
 	execution_hazard_barrier();