From: Fabio Estevam <festevam@denx.de>
Date: Tue, 18 Jan 2022 20:39:50 +0000 (-0300)
Subject: smegw01: Update DDR initialization
X-Git-Url: http://git.dujemihanovic.xyz/login.html?a=commitdiff_plain;h=9376d799debb3d8fb9b5ddbb88dd21548e0157bc;p=u-boot.git

smegw01: Update DDR initialization

Sync with the latest DDR initialization from Phytec, which
uses version 1.2 of NXP's i.MX7D DRAM Register Programming Aid
spreadsheet.

This updated DDR initialization fixes occasional system freeze.

Signed-off-by: Fabio Estevam <festevam@denx.de>
---

diff --git a/board/storopack/smegw01/imximage.cfg b/board/storopack/smegw01/imximage.cfg
index c7fa06996c..5ebeea56a7 100644
--- a/board/storopack/smegw01/imximage.cfg
+++ b/board/storopack/smegw01/imximage.cfg
@@ -44,57 +44,80 @@ BOOT_FROM	sd
 
 /* DDR initialization came from Phytec */
 DATA 4 0x30340004 0x4F400005
+/* Clear then set bit30 to ensure exit from DDR retention */
 DATA 4 0x30360388 0x40000000
 DATA 4 0x30360384 0x40000000
+
+/* deassert presetn */
 DATA 4 0x30391000 0x00000002
+
+/* DDR Controller Regs */
 DATA 4 0x307a0000 0x01040001
-DATA 4 0x307a01a0 0x80400003
-DATA 4 0x307a01a4 0x00100020
-DATA 4 0x307a01a8 0x80100004
-DATA 4 0x307a0064 0x0040002b
+DATA 4 0x307a0064 0x00400046
 DATA 4 0x307a0490 0x00000001
-DATA 4 0x307a00d0 0x00020083
 DATA 4 0x307a00d4 0x00690000
+DATA 4 0x307a00d0 0x00020083
 DATA 4 0x307a00dc 0x09300004
-DATA 4 0x307a00e0 0x04080000
+DATA 4 0x307a00e0 0x04480000
 DATA 4 0x307a00e4 0x00100004
 DATA 4 0x307a00f4 0x0000033f
-DATA 4 0x307a0100 0x090b1109
-DATA 4 0x307a0104 0x0007020d
+DATA 4 0x307a0100 0x090e110a
+DATA 4 0x307a0104 0x0007020e
 DATA 4 0x307a0108 0x03040407
 DATA 4 0x307a010c 0x00002006
-DATA 4 0x307a0110 0x04020205
+DATA 4 0x307a0110 0x04020304
 DATA 4 0x307a0114 0x03030202
-DATA 4 0x307a0120 0x00000802
+DATA 4 0x307a0120 0x00000803
 DATA 4 0x307a0180 0x00800020
-DATA 4 0x307a0184 0x02000100
 DATA 4 0x307a0190 0x02098204
 DATA 4 0x307a0194 0x00030303
-DATA 4 0x307a0200 0x00001f15
+DATA 4 0x307a01a0 0x80400003
+DATA 4 0x307a01a4 0x00100020
+DATA 4 0x307a01a8 0x80100004
+DATA 4 0x307a0200 0x0000001f
 DATA 4 0x307a0204 0x00080808
+DATA 4 0x307a020c 0x00000000
 DATA 4 0x307a0210 0x00000f0f
 DATA 4 0x307a0214 0x07070707
-DATA 4 0x307a0218 0x0f0f0707
+DATA 4 0x307a0218 0x0f070707
 DATA 4 0x307a0240 0x06000604
 DATA 4 0x307a0244 0x00000001
+
+/* deassert presetn */
 DATA 4 0x30391000 0x00000000
+
+/* PHY Controller Regs */
 DATA 4 0x30790000 0x17420f40
 DATA 4 0x30790004 0x10210100
 DATA 4 0x30790010 0x00060807
 DATA 4 0x307900b0 0x1010007e
 DATA 4 0x3079009c 0x00000d6e
-DATA 4 0x30790020 0x0a0a0a0a
-DATA 4 0x30790030 0x06060606
+/* write leveling values for each byte lane */
+DATA 4 0x3079006c 0x06090108
+/* write leveling resync cycle */
+DATA 4 0x30790078 0x00000001
+DATA 4 0x30790078 0x00000000
+DATA 4 0x30790030 0x08080808
+DATA 4 0x30790020 0x08080808
 DATA 4 0x30790050 0x01000010
 DATA 4 0x30790050 0x00000010
+DATA 4 0x30790018 0x0000000f
+
+/* start manual ZQ */
 DATA 4 0x307900c0 0x0e407304
 DATA 4 0x307900c0 0x0e447304
 DATA 4 0x307900c0 0x0e447306
-CHECK_BITS_SET 4 0x307900c4 0x1
 DATA 4 0x307900c0 0x0e447304
+
+CHECK_BITS_SET 4 0x307900c4 0x1
+
+/* end manual ZQ */
 DATA 4 0x307900c0 0x0e407304
+
+/* final init sequence */
 DATA 4 0x30384130 0x00000000
 DATA 4 0x30340020 0x00000178
 DATA 4 0x30384130 0x00000002
 DATA 4 0x30790018 0x0000000f
+
 CHECK_BITS_SET 4 0x307a0004 0x1