From: Peng Fan <peng.fan@nxp.com>
Date: Tue, 26 Jul 2022 08:40:39 +0000 (+0800)
Subject: imx: add basic i.MX9 support
X-Git-Url: http://git.dujemihanovic.xyz/login.html?a=commitdiff_plain;h=881df6ed84c965608292d4b0e44e53e4dc821b09;p=u-boot.git

imx: add basic i.MX9 support

Add i.MX9 Kconfig and basic files for the new SoC

Signed-off-by: Peng Fan <peng.fan@nxp.com>
---

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
index d4fc83318a..2802b9b3fa 100644
--- a/arch/arm/Kconfig
+++ b/arch/arm/Kconfig
@@ -908,6 +908,15 @@ config ARCH_IMX8ULP
 	imply CMD_DM
 	imply DM_EVENT
 
+config ARCH_IMX9
+	bool "NXP i.MX9 platform"
+	select ARM64
+	select DM
+	select MACH_IMX
+	select SUPPORT_SPL
+	imply CMD_DM
+	imply DM_EVENT
+
 config ARCH_IMXRT
 	bool "NXP i.MXRT platform"
 	select CPU_V7M
@@ -2228,6 +2237,8 @@ source "arch/arm/mach-imx/imx8m/Kconfig"
 
 source "arch/arm/mach-imx/imx8ulp/Kconfig"
 
+source "arch/arm/mach-imx/imx9/Kconfig"
+
 source "arch/arm/mach-imx/imxrt/Kconfig"
 
 source "arch/arm/mach-imx/mxs/Kconfig"
diff --git a/arch/arm/include/asm/arch-imx/cpu.h b/arch/arm/include/asm/arch-imx/cpu.h
index 4f63803765..d54e6e6335 100644
--- a/arch/arm/include/asm/arch-imx/cpu.h
+++ b/arch/arm/include/asm/arch-imx/cpu.h
@@ -59,6 +59,7 @@
 
 #define MXC_CPU_MX7ULP		0xE1 /* Temporally hard code */
 #define MXC_CPU_VF610		0xF6 /* dummy ID */
+#define MXC_CPU_IMX93		0xC1 /* dummy ID */
 
 #define MXC_SOC_MX6		0x60
 #define MXC_SOC_MX7		0x70
@@ -66,6 +67,7 @@
 #define MXC_SOC_IMX8		0x90 /* dummy */
 #define MXC_SOC_IMXRT		0xB0 /* dummy */
 #define MXC_SOC_MX7ULP		0xE0 /* dummy */
+#define MXC_SOC_IMX9		0xC0 /* dummy */
 
 #define CHIP_REV_1_0            0x10
 #define CHIP_REV_1_1            0x11
diff --git a/arch/arm/include/asm/arch-imx9/clock.h b/arch/arm/include/asm/arch-imx9/clock.h
new file mode 100644
index 0000000000..e69de29bb2
diff --git a/arch/arm/include/asm/arch-imx9/gpio.h b/arch/arm/include/asm/arch-imx9/gpio.h
new file mode 100644
index 0000000000..e69de29bb2
diff --git a/arch/arm/include/asm/arch-imx9/imx-regs.h b/arch/arm/include/asm/arch-imx9/imx-regs.h
new file mode 100644
index 0000000000..2adbdadf03
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx9/imx-regs.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2022 NXP
+ */
+
+#ifndef __ASM_ARCH_IMX9_REGS_H__
+#define __ASM_ARCH_IMX9_REGS_H__
+
+#define ARCH_MXC
+
+#define IOMUXC_BASE_ADDR 0x443C0000UL
+
+#endif
diff --git a/arch/arm/include/asm/arch-imx9/imx93_pins.h b/arch/arm/include/asm/arch-imx9/imx93_pins.h
new file mode 100644
index 0000000000..f13aef5619
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx9/imx93_pins.h
@@ -0,0 +1,729 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2022 NXP
+ */
+
+#ifndef __ASM_ARCH_IMX93_PINS_H__
+#define __ASM_ARCH_IMX93_PINS_H__
+
+#include <asm/mach-imx/iomux-v3.h>
+
+enum {
+	MX93_PAD_DAP_TDI__JTAG_MUX_TDI			= IOMUX_PAD(0x1B0, 0x0000, 0, 0x3D8, 0, 0),
+	MX93_PAD_DAP_TDI__MQS2_LEFT			= IOMUX_PAD(0x1B0, 0x0000, 1, 0x0000, 0, 0),
+	MX93_PAD_DAP_TDI__CAN2_TX			= IOMUX_PAD(0x1B0, 0x0000, 3, 0x0000, 0, 0),
+	MX93_PAD_DAP_TDI__FLEXIO2_FLEXIO30		= IOMUX_PAD(0x1B0, 0x0000, 4, 0x0000, 0, 0),
+	MX93_PAD_DAP_TDI__GPIO3_IO28			= IOMUX_PAD(0x1B0, 0x0000, 5, 0x0000, 0, 0),
+	MX93_PAD_DAP_TDI__LPUART5_RX			= IOMUX_PAD(0x1B0, 0x0000, 6, 0x430, 0, 0),
+
+	MX93_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS		= IOMUX_PAD(0x1B4, 0x0004, 0, 0x3DC, 0, 0),
+	MX93_PAD_DAP_TMS_SWDIO__FLEXIO2_FLEXIO31	= IOMUX_PAD(0x1B4, 0x0004, 4, 0x0000, 0, 0),
+	MX93_PAD_DAP_TMS_SWDIO__GPIO3_IO29		= IOMUX_PAD(0x1B4, 0x0004, 5, 0x0000, 0, 0),
+	MX93_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B		= IOMUX_PAD(0x1B4, 0x0004, 6, 0x0000, 0, 0),
+
+	MX93_PAD_DAP_TCLK_SWCLK__JTAG_MUX_TCK		= IOMUX_PAD(0x1B8, 0x0008, 0, 0x3D4, 0, 0),
+	MX93_PAD_DAP_TCLK_SWCLK__FLEXIO1_FLEXIO30	= IOMUX_PAD(0x1B8, 0x0008, 4, 0x0000, 0, 0),
+	MX93_PAD_DAP_TCLK_SWCLK__GPIO3_IO30		= IOMUX_PAD(0x1B8, 0x0008, 5, 0x0000, 0, 0),
+	MX93_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B		= IOMUX_PAD(0x1B8, 0x0008, 6, 0x42C, 0, 0),
+
+	MX93_PAD_DAP_TDO_TRACESWO__JTAG_MUX_TDO		= IOMUX_PAD(0x1BC, 0x000C, 0, 0x0000, 0, 0),
+	MX93_PAD_DAP_TDO_TRACESWO__MQS2_RIGHT		= IOMUX_PAD(0x1BC, 0x000C, 1, 0x0000, 0, 0),
+	MX93_PAD_DAP_TDO_TRACESWO__CAN2_RX		= IOMUX_PAD(0x1BC, 0x000C, 3, 0x364, 0, 0),
+	MX93_PAD_DAP_TDO_TRACESWO__FLEXIO1_FLEXIO31	= IOMUX_PAD(0x1BC, 0x000C, 4, 0x0000, 0, 0),
+	MX93_PAD_DAP_TDO_TRACESWO__GPIO3_IO31		= IOMUX_PAD(0x1BC, 0x000C, 5, 0x0000, 0, 0),
+	MX93_PAD_DAP_TDO_TRACESWO__LPUART5_TX		= IOMUX_PAD(0x1BC, 0x000C, 6, 0x434, 0, 0),
+
+	MX93_PAD_GPIO_IO00__GPIO2_IO00			= IOMUX_PAD(0x1C0, 0x0010, 0, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO00__LPI2C3_SDA			= IOMUX_PAD(0x1C0, 0x0010, 1, 0x3E4, 0, 0),
+	MX93_PAD_GPIO_IO00__MEDIAMIX_CAM_CLK		= IOMUX_PAD(0x1C0, 0x0010, 2, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK		= IOMUX_PAD(0x1C0, 0x0010, 3, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO00__LPSPI6_PCS0			= IOMUX_PAD(0x1C0, 0x0010, 4, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO00__LPUART5_TX			= IOMUX_PAD(0x1C0, 0x0010, 5, 0x434, 1, 0),
+	MX93_PAD_GPIO_IO00__LPI2C5_SDA			= IOMUX_PAD(0x1C0, 0x0010, 6, 0x3EC, 0, 0),
+	MX93_PAD_GPIO_IO00__FLEXIO1_FLEXIO00		= IOMUX_PAD(0x1C0, 0x0010, 7, 0x36C, 0, 0),
+
+	MX93_PAD_GPIO_IO01__GPIO2_IO01			= IOMUX_PAD(0x1C4, 0x0014, 0, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO01__LPI2C3_SCL			= IOMUX_PAD(0x1C4, 0x0014, 1, 0x3E0, 0, 0),
+	MX93_PAD_GPIO_IO01__MEDIAMIX_CAM_DATA00		= IOMUX_PAD(0x1C4, 0x0014, 2, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO01__MEDIAMIX_DISP_DE		= IOMUX_PAD(0x1C4, 0x0014, 3, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO01__LPSPI6_SIN			= IOMUX_PAD(0x1C4, 0x0014, 4, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO01__LPUART5_RX			= IOMUX_PAD(0x1C4, 0x0014, 5, 0x430, 1, 0),
+	MX93_PAD_GPIO_IO01__LPI2C5_SCL			= IOMUX_PAD(0x1C4, 0x0014, 6, 0x3E8, 0, 0),
+	MX93_PAD_GPIO_IO01__FLEXIO1_FLEXIO01		= IOMUX_PAD(0x1C4, 0x0014, 7, 0x370, 0, 0),
+
+	MX93_PAD_GPIO_IO02__GPIO2_IO02			= IOMUX_PAD(0x1C8, 0x0018, 0, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO02__LPI2C4_SDA			= IOMUX_PAD(0x1C8, 0x0018, 1, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO02__MEDIAMIX_CAM_VSYNC		= IOMUX_PAD(0x1C8, 0x0018, 2, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC		= IOMUX_PAD(0x1C8, 0x0018, 3, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO02__LPSPI6_SOUT			= IOMUX_PAD(0x1C8, 0x0018, 4, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO02__LPUART5_CTS_B		= IOMUX_PAD(0x1C8, 0x0018, 5, 0x42C, 1, 0),
+	MX93_PAD_GPIO_IO02__LPI2C6_SDA			= IOMUX_PAD(0x1C8, 0x0018, 6, 0x3F4, 0, 0),
+	MX93_PAD_GPIO_IO02__FLEXIO1_FLEXIO02		= IOMUX_PAD(0x1C8, 0x0018, 7, 0x374, 0, 0),
+
+	MX93_PAD_GPIO_IO03__GPIO2_IO03			= IOMUX_PAD(0x1CC, 0x001C, 0, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO03__LPI2C4_SCL			= IOMUX_PAD(0x1CC, 0x001C, 1, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO03__MEDIAMIX_CAM_HSYNC		= IOMUX_PAD(0x1CC, 0x001C, 2, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC		= IOMUX_PAD(0x1CC, 0x001C, 3, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO03__LPSPI6_SCK			= IOMUX_PAD(0x1CC, 0x001C, 4, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO03__LPUART5_RTS_B		= IOMUX_PAD(0x1CC, 0x001C, 5, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO03__LPI2C6_SCL			= IOMUX_PAD(0x1CC, 0x001C, 6, 0x3F0, 0, 0),
+	MX93_PAD_GPIO_IO03__FLEXIO1_FLEXIO03		= IOMUX_PAD(0x1CC, 0x001C, 7, 0x378, 0, 0),
+
+	MX93_PAD_GPIO_IO04__GPIO2_IO04			= IOMUX_PAD(0x1D0, 0x0020, 0, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO04__TPM3_CH0			= IOMUX_PAD(0x1D0, 0x0020, 1, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO04__PDM_CLK			= IOMUX_PAD(0x1D0, 0x0020, 2, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA00	= IOMUX_PAD(0x1D0, 0x0020, 3, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO04__LPSPI7_PCS0			= IOMUX_PAD(0x1D0, 0x0020, 4, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO04__LPUART6_TX			= IOMUX_PAD(0x1D0, 0x0020, 5, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO04__LPI2C6_SDA			= IOMUX_PAD(0x1D0, 0x0020, 6, 0x3F4, 1, 0),
+	MX93_PAD_GPIO_IO04__FLEXIO1_FLEXIO04		= IOMUX_PAD(0x1D0, 0x0020, 7, 0x37C, 0, 0),
+
+	MX93_PAD_GPIO_IO05__GPIO2_IO05			= IOMUX_PAD(0x1D4, 0x0024, 0, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO05__TPM4_CH0			= IOMUX_PAD(0x1D4, 0x0024, 1, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO05__PDM_BIT_STREAM00		= IOMUX_PAD(0x1D4, 0x0024, 2, 0x438, 0, 0),
+	MX93_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA01	= IOMUX_PAD(0x1D4, 0x0024, 3, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO05__LPSPI7_SIN			= IOMUX_PAD(0x1D4, 0x0024, 4, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO05__LPUART6_RX			= IOMUX_PAD(0x1D4, 0x0024, 5, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO05__LPI2C6_SCL			= IOMUX_PAD(0x1D4, 0x0024, 6, 0x3F0, 1, 0),
+	MX93_PAD_GPIO_IO05__FLEXIO1_FLEXIO05		= IOMUX_PAD(0x1D4, 0x0024, 7, 0x380, 0, 0),
+
+	MX93_PAD_GPIO_IO06__GPIO2_IO06			= IOMUX_PAD(0x1D8, 0x0028, 0, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO06__TPM5_CH0			= IOMUX_PAD(0x1D8, 0x0028, 1, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO06__PDM_BIT_STREAM01		= IOMUX_PAD(0x1D8, 0x0028, 2, 0x43C, 0, 0),
+	MX93_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA02	= IOMUX_PAD(0x1D8, 0x0028, 3, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO06__LPSPI7_SOUT			= IOMUX_PAD(0x1D8, 0x0028, 4, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO06__LPUART6_CTS_B		= IOMUX_PAD(0x1D8, 0x0028, 5, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO06__LPI2C7_SDA			= IOMUX_PAD(0x1D8, 0x0028, 6, 0x3FC, 0, 0),
+	MX93_PAD_GPIO_IO06__FLEXIO1_FLEXIO06		= IOMUX_PAD(0x1D8, 0x0028, 7, 0x384, 0, 0),
+
+	MX93_PAD_GPIO_IO07__GPIO2_IO07			= IOMUX_PAD(0x1DC, 0x002C, 0, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO07__LPSPI3_PCS1			= IOMUX_PAD(0x1DC, 0x002C, 1, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO07__MEDIAMIX_CAM_DATA01		= IOMUX_PAD(0x1DC, 0x002C, 2, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA03	= IOMUX_PAD(0x1DC, 0x002C, 3, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO07__LPSPI7_SCK			= IOMUX_PAD(0x1DC, 0x002C, 4, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO07__LPUART6_RTS_B		= IOMUX_PAD(0x1DC, 0x002C, 5, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO07__LPI2C7_SCL			= IOMUX_PAD(0x1DC, 0x002C, 6, 0x3F8, 0, 0),
+	MX93_PAD_GPIO_IO07__FLEXIO1_FLEXIO07		= IOMUX_PAD(0x1DC, 0x002C, 7, 0x388, 0, 0),
+
+	MX93_PAD_GPIO_IO08__GPIO2_IO08			= IOMUX_PAD(0x1E0, 0x0030, 0, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO08__LPSPI3_PCS0			= IOMUX_PAD(0x1E0, 0x0030, 1, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO08__MEDIAMIX_CAM_DATA02		= IOMUX_PAD(0x1E0, 0x0030, 2, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA04	= IOMUX_PAD(0x1E0, 0x0030, 3, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO08__TPM6_CH0			= IOMUX_PAD(0x1E0, 0x0030, 4, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO08__LPUART7_TX			= IOMUX_PAD(0x1E0, 0x0030, 5, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO08__LPI2C7_SDA			= IOMUX_PAD(0x1E0, 0x0030, 6, 0x3FC, 1, 0),
+	MX93_PAD_GPIO_IO08__FLEXIO1_FLEXIO08		= IOMUX_PAD(0x1E0, 0x0030, 7, 0x38C, 0, 0),
+
+	MX93_PAD_GPIO_IO09__GPIO2_IO09			= IOMUX_PAD(0x1E4, 0x0034, 0, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO09__LPSPI3_SIN			= IOMUX_PAD(0x1E4, 0x0034, 1, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO09__MEDIAMIX_CAM_DATA03		= IOMUX_PAD(0x1E4, 0x0034, 2, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA05	= IOMUX_PAD(0x1E4, 0x0034, 3, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO09__TPM3_EXTCLK			= IOMUX_PAD(0x1E4, 0x0034, 4, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO09__LPUART7_RX			= IOMUX_PAD(0x1E4, 0x0034, 5, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO09__LPI2C7_SCL			= IOMUX_PAD(0x1E4, 0x0034, 6, 0x3F8, 1, 0),
+	MX93_PAD_GPIO_IO09__FLEXIO1_FLEXIO09		= IOMUX_PAD(0x1E4, 0x0034, 7, 0x390, 0, 0),
+
+	MX93_PAD_GPIO_IO10__GPIO2_IO10			= IOMUX_PAD(0x1E8, 0x0038, 0, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO10__LPSPI3_SOUT			= IOMUX_PAD(0x1E8, 0x0038, 1, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO10__MEDIAMIX_CAM_DATA04		= IOMUX_PAD(0x1E8, 0x0038, 2, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA06	= IOMUX_PAD(0x1E8, 0x0038, 3, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO10__TPM4_EXTCLK			= IOMUX_PAD(0x1E8, 0x0038, 4, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO10__LPUART7_CTS_B		= IOMUX_PAD(0x1E8, 0x0038, 5, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO10__LPI2C8_SDA			= IOMUX_PAD(0x1E8, 0x0038, 6, 0x404, 0, 0),
+	MX93_PAD_GPIO_IO10__FLEXIO1_FLEXIO10		= IOMUX_PAD(0x1E8, 0x0038, 7, 0x394, 0, 0),
+
+	MX93_PAD_GPIO_IO11__GPIO2_IO11			= IOMUX_PAD(0x1EC, 0x003C, 0, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO11__LPSPI3_SCK			= IOMUX_PAD(0x1EC, 0x003C, 1, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO11__MEDIAMIX_CAM_DATA05		= IOMUX_PAD(0x1EC, 0x003C, 2, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA07	= IOMUX_PAD(0x1EC, 0x003C, 3, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO11__TPM5_EXTCLK			= IOMUX_PAD(0x1EC, 0x003C, 4, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO11__LPUART7_RTS_B		= IOMUX_PAD(0x1EC, 0x003C, 5, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO11__LPI2C8_SCL			= IOMUX_PAD(0x1EC, 0x003C, 6, 0x400, 0, 0),
+	MX93_PAD_GPIO_IO11__FLEXIO1_FLEXIO11		= IOMUX_PAD(0x1EC, 0x003C, 7, 0x398, 0, 0),
+
+	MX93_PAD_GPIO_IO12__GPIO2_IO12			= IOMUX_PAD(0x1F0, 0x0040, 0, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO12__TPM3_CH2			= IOMUX_PAD(0x1F0, 0x0040, 1, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO12__PDM_BIT_STREAM02		= IOMUX_PAD(0x1F0, 0x0040, 2, 0x440, 0, 0),
+	MX93_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA08	= IOMUX_PAD(0x1F0, 0x0040, 3, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO12__LPSPI8_PCS0			= IOMUX_PAD(0x1F0, 0x0040, 4, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO12__LPUART8_TX			= IOMUX_PAD(0x1F0, 0x0040, 5, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO12__LPI2C8_SDA			= IOMUX_PAD(0x1F0, 0x0040, 6, 0x404, 1, 0),
+	MX93_PAD_GPIO_IO12__SAI3_RX_SYNC		= IOMUX_PAD(0x1F0, 0x0040, 7, 0x450, 0, 0),
+
+	MX93_PAD_GPIO_IO13__GPIO2_IO13			= IOMUX_PAD(0x1F4, 0x0044, 0, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO13__TPM4_CH2			= IOMUX_PAD(0x1F4, 0x0044, 1, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO13__PDM_BIT_STREAM03		= IOMUX_PAD(0x1F4, 0x0044, 2, 0x444, 0, 0),
+	MX93_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA09	= IOMUX_PAD(0x1F4, 0x0044, 3, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO13__LPSPI8_SIN			= IOMUX_PAD(0x1F4, 0x0044, 4, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO13__LPUART8_RX			= IOMUX_PAD(0x1F4, 0x0044, 5, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO13__LPI2C8_SCL			= IOMUX_PAD(0x1F4, 0x0044, 6, 0x400, 1, 0),
+	MX93_PAD_GPIO_IO13__FLEXIO1_FLEXIO13		= IOMUX_PAD(0x1F4, 0x0044, 7, 0x39C, 0, 0),
+
+	MX93_PAD_GPIO_IO14__GPIO2_IO14			= IOMUX_PAD(0x1F8, 0x0048, 0, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO14__LPUART3_TX			= IOMUX_PAD(0x1F8, 0x0048, 1, 0x41C, 0, 0),
+	MX93_PAD_GPIO_IO14__MEDIAMIX_CAM_DATA06		= IOMUX_PAD(0x1F8, 0x0048, 2, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10	= IOMUX_PAD(0x1F8, 0x0048, 3, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO14__LPSPI8_SOUT			= IOMUX_PAD(0x1F8, 0x0048, 4, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO14__LPUART8_CTS_B		= IOMUX_PAD(0x1F8, 0x0048, 5, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO14__LPUART4_TX			= IOMUX_PAD(0x1F8, 0x0048, 6, 0x428, 0, 0),
+	MX93_PAD_GPIO_IO14__FLEXIO1_FLEXIO14		= IOMUX_PAD(0x1F8, 0x0048, 7, 0x3A0, 0, 0),
+
+	MX93_PAD_GPIO_IO15__GPIO2_IO15			= IOMUX_PAD(0x1FC, 0x004C, 0, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO15__LPUART3_RX			= IOMUX_PAD(0x1FC, 0x004C, 1, 0x418, 0, 0),
+	MX93_PAD_GPIO_IO15__MEDIAMIX_CAM_DATA07		= IOMUX_PAD(0x1FC, 0x004C, 2, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11	= IOMUX_PAD(0x1FC, 0x004C, 3, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO15__LPSPI8_SCK			= IOMUX_PAD(0x1FC, 0x004C, 4, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO15__LPUART8_RTS_B		= IOMUX_PAD(0x1FC, 0x004C, 5, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO15__LPUART4_RX			= IOMUX_PAD(0x1FC, 0x004C, 6, 0x424, 0, 0),
+	MX93_PAD_GPIO_IO15__FLEXIO1_FLEXIO15		= IOMUX_PAD(0x1FC, 0x004C, 7, 0x3A4, 0, 0),
+
+	MX93_PAD_GPIO_IO16__GPIO2_IO16			= IOMUX_PAD(0x200, 0x0050, 0, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO16__SAI3_TX_BCLK		= IOMUX_PAD(0x200, 0x0050, 1, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO16__PDM_BIT_STREAM02		= IOMUX_PAD(0x200, 0x0050, 2, 0x440, 1, 0),
+	MX93_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12	= IOMUX_PAD(0x200, 0x0050, 3, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO16__LPUART3_CTS_B		= IOMUX_PAD(0x200, 0x0050, 4, 0x414, 0, 0),
+	MX93_PAD_GPIO_IO16__LPSPI4_PCS2			= IOMUX_PAD(0x200, 0x0050, 5, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO16__LPUART4_CTS_B		= IOMUX_PAD(0x200, 0x0050, 6, 0x420, 0, 0),
+	MX93_PAD_GPIO_IO16__FLEXIO1_FLEXIO16		= IOMUX_PAD(0x200, 0x0050, 7, 0x3A8, 0, 0),
+
+	MX93_PAD_GPIO_IO17__GPIO2_IO17			= IOMUX_PAD(0x204, 0x0054, 0, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO17__SAI3_MCLK			= IOMUX_PAD(0x204, 0x0054, 1, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO17__MEDIAMIX_CAM_DATA08		= IOMUX_PAD(0x204, 0x0054, 2, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO17__MEDIAMIX_DISP_DATA13	= IOMUX_PAD(0x204, 0x0054, 3, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO17__LPUART3_RTS_B		= IOMUX_PAD(0x204, 0x0054, 4, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO17__LPSPI4_PCS1			= IOMUX_PAD(0x204, 0x0054, 5, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO17__LPUART4_RTS_B		= IOMUX_PAD(0x204, 0x0054, 6, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO17__FLEXIO1_FLEXIO17		= IOMUX_PAD(0x204, 0x0054, 7, 0x3AC, 0, 0),
+
+	MX93_PAD_GPIO_IO18__GPIO2_IO18			= IOMUX_PAD(0x208, 0x0058, 0, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO18__SAI3_RX_BCLK		= IOMUX_PAD(0x208, 0x0058, 1, 0x44C, 0, 0),
+	MX93_PAD_GPIO_IO18__MEDIAMIX_CAM_DATA09		= IOMUX_PAD(0x208, 0x0058, 2, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14	= IOMUX_PAD(0x208, 0x0058, 3, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO18__LPSPI5_PCS0			= IOMUX_PAD(0x208, 0x0058, 4, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO18__LPSPI4_PCS0			= IOMUX_PAD(0x208, 0x0058, 5, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO18__TPM5_CH2			= IOMUX_PAD(0x208, 0x0058, 6, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO18__FLEXIO1_FLEXIO18		= IOMUX_PAD(0x208, 0x0058, 7, 0x3B0, 0, 0),
+
+	MX93_PAD_GPIO_IO19__GPIO2_IO19			= IOMUX_PAD(0x20C, 0x005C, 0, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO19__SAI3_RX_SYNC		= IOMUX_PAD(0x20C, 0x005C, 1, 0x450, 1, 0),
+	MX93_PAD_GPIO_IO19__PDM_BIT_STREAM03		= IOMUX_PAD(0x20C, 0x005C, 2, 0x444, 1, 0),
+	MX93_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15	= IOMUX_PAD(0x20C, 0x005C, 3, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO19__LPSPI5_SIN			= IOMUX_PAD(0x20C, 0x005C, 4, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO19__LPSPI4_SIN			= IOMUX_PAD(0x20C, 0x005C, 5, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO19__TPM6_CH2			= IOMUX_PAD(0x20C, 0x005C, 6, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO19__SAI3_TX_DATA00		= IOMUX_PAD(0x20C, 0x005C, 7, 0x0000, 0, 0),
+
+	MX93_PAD_GPIO_IO20__GPIO2_IO20			= IOMUX_PAD(0x210, 0x0060, 0, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO20__SAI3_RX_DATA00		= IOMUX_PAD(0x210, 0x0060, 1, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO20__PDM_BIT_STREAM00		= IOMUX_PAD(0x210, 0x0060, 2, 0x438, 1, 0),
+	MX93_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16	= IOMUX_PAD(0x210, 0x0060, 3, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO20__LPSPI5_SOUT			= IOMUX_PAD(0x210, 0x0060, 4, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO20__LPSPI4_SOUT			= IOMUX_PAD(0x210, 0x0060, 5, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO20__TPM3_CH1			= IOMUX_PAD(0x210, 0x0060, 6, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO20__FLEXIO1_FLEXIO20		= IOMUX_PAD(0x210, 0x0060, 7, 0x3B4, 0, 0),
+
+	MX93_PAD_GPIO_IO21__GPIO2_IO21			= IOMUX_PAD(0x214, 0x0064, 0, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO21__SAI3_TX_DATA00		= IOMUX_PAD(0x214, 0x0064, 1, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO21__PDM_CLK			= IOMUX_PAD(0x214, 0x0064, 2, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO21__MEDIAMIX_DISP_DATA17	= IOMUX_PAD(0x214, 0x0064, 3, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO21__LPSPI5_SCK			= IOMUX_PAD(0x214, 0x0064, 4, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO21__LPSPI4_SCK			= IOMUX_PAD(0x214, 0x0064, 5, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO21__TPM4_CH1			= IOMUX_PAD(0x214, 0x0064, 6, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO21__SAI3_RX_BCLK		= IOMUX_PAD(0x214, 0x0064, 7, 0x44C, 1, 0),
+
+	MX93_PAD_GPIO_IO22__GPIO2_IO22			= IOMUX_PAD(0x218, 0x0068, 0, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO22__USDHC3_CLK			= IOMUX_PAD(0x218, 0x0068, 1, 0x458, 0, 0),
+	MX93_PAD_GPIO_IO22__SPDIF_IN			= IOMUX_PAD(0x218, 0x0068, 2, 0x454, 0, 0),
+	MX93_PAD_GPIO_IO22__MEDIAMIX_DISP_DATA18	= IOMUX_PAD(0x218, 0x0068, 3, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO22__TPM5_CH1			= IOMUX_PAD(0x218, 0x0068, 4, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO22__TPM6_EXTCLK			= IOMUX_PAD(0x218, 0x0068, 5, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO22__LPI2C5_SDA			= IOMUX_PAD(0x218, 0x0068, 6, 0x3EC, 1, 0),
+	MX93_PAD_GPIO_IO22__FLEXIO1_FLEXIO22		= IOMUX_PAD(0x218, 0x0068, 7, 0x3B8, 0, 0),
+
+	MX93_PAD_GPIO_IO23__GPIO2_IO23			= IOMUX_PAD(0x21C, 0x006C, 0, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO23__USDHC3_CMD			= IOMUX_PAD(0x21C, 0x006C, 1, 0x45C, 0, 0),
+	MX93_PAD_GPIO_IO23__SPDIF_OUT			= IOMUX_PAD(0x21C, 0x006C, 2, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO23__MEDIAMIX_DISP_DATA19	= IOMUX_PAD(0x21C, 0x006C, 3, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO23__TPM6_CH1			= IOMUX_PAD(0x21C, 0x006C, 4, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO23__LPI2C5_SCL			= IOMUX_PAD(0x21C, 0x006C, 6, 0x3E8, 1, 0),
+	MX93_PAD_GPIO_IO23__FLEXIO1_FLEXIO23		= IOMUX_PAD(0x21C, 0x006C, 7, 0x3BC, 0, 0),
+
+	MX93_PAD_GPIO_IO24__GPIO2_IO24			= IOMUX_PAD(0x220, 0x0070, 0, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO24__USDHC3_DATA0		= IOMUX_PAD(0x220, 0x0070, 1, 0x460, 0, 0),
+	MX93_PAD_GPIO_IO24__MEDIAMIX_DISP_DATA20	= IOMUX_PAD(0x220, 0x0070, 3, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO24__TPM3_CH3			= IOMUX_PAD(0x220, 0x0070, 4, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO24__JTAG_MUX_TDO		= IOMUX_PAD(0x220, 0x0070, 5, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO24__LPSPI6_PCS1			= IOMUX_PAD(0x220, 0x0070, 6, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO24__FLEXIO1_FLEXIO24		= IOMUX_PAD(0x220, 0x0070, 7, 0x3C0, 0, 0),
+
+	MX93_PAD_GPIO_IO25__GPIO2_IO25			= IOMUX_PAD(0x224, 0x0074, 0, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO25__USDHC3_DATA1		= IOMUX_PAD(0x224, 0x0074, 1, 0x464, 0, 0),
+	MX93_PAD_GPIO_IO25__CAN2_TX			= IOMUX_PAD(0x224, 0x0074, 2, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO25__MEDIAMIX_DISP_DATA21	= IOMUX_PAD(0x224, 0x0074, 3, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO25__TPM4_CH3			= IOMUX_PAD(0x224, 0x0074, 4, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO25__JTAG_MUX_TCK		= IOMUX_PAD(0x224, 0x0074, 5, 0x3D4, 1, 0),
+	MX93_PAD_GPIO_IO25__LPSPI7_PCS1			= IOMUX_PAD(0x224, 0x0074, 6, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO25__FLEXIO1_FLEXIO25		= IOMUX_PAD(0x224, 0x0074, 7, 0x3C4, 0, 0),
+
+	MX93_PAD_GPIO_IO26__GPIO2_IO26			= IOMUX_PAD(0x228, 0x0078, 0, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO26__USDHC3_DATA2		= IOMUX_PAD(0x228, 0x0078, 1, 0x468, 0, 0),
+	MX93_PAD_GPIO_IO26__PDM_BIT_STREAM01		= IOMUX_PAD(0x228, 0x0078, 2, 0x43C, 1, 0),
+	MX93_PAD_GPIO_IO26__MEDIAMIX_DISP_DATA22	= IOMUX_PAD(0x228, 0x0078, 3, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO26__TPM5_CH3			= IOMUX_PAD(0x228, 0x0078, 4, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO26__JTAG_MUX_TDI		= IOMUX_PAD(0x228, 0x0078, 5, 0x3D8, 1, 0),
+	MX93_PAD_GPIO_IO26__LPSPI8_PCS1			= IOMUX_PAD(0x228, 0x0078, 6, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO26__SAI3_TX_SYNC		= IOMUX_PAD(0x228, 0x0078, 7, 0x0000, 0, 0),
+
+	MX93_PAD_GPIO_IO27__GPIO2_IO27			= IOMUX_PAD(0x22C, 0x007C, 0, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO27__USDHC3_DATA3		= IOMUX_PAD(0x22C, 0x007C, 1, 0x46C, 0, 0),
+	MX93_PAD_GPIO_IO27__CAN2_RX			= IOMUX_PAD(0x22C, 0x007C, 2, 0x364, 1, 0),
+	MX93_PAD_GPIO_IO27__MEDIAMIX_DISP_DATA23	= IOMUX_PAD(0x22C, 0x007C, 3, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO27__TPM6_CH3			= IOMUX_PAD(0x22C, 0x007C, 4, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO27__JTAG_MUX_TMS		= IOMUX_PAD(0x22C, 0x007C, 5, 0x3DC, 1, 0),
+	MX93_PAD_GPIO_IO27__LPSPI5_PCS1			= IOMUX_PAD(0x22C, 0x007C, 6, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO27__FLEXIO1_FLEXIO27		= IOMUX_PAD(0x22C, 0x007C, 7, 0x3C8, 0, 0),
+
+	MX93_PAD_GPIO_IO28__GPIO2_IO28			= IOMUX_PAD(0x230, 0x0080, 0, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO28__LPI2C3_SDA			= IOMUX_PAD(0x230, 0x0080, 1, 0x3E4, 1, 0),
+	MX93_PAD_GPIO_IO28__FLEXIO1_FLEXIO28		= IOMUX_PAD(0x230, 0x0080, 7, 0x0000, 0, 0),
+
+	MX93_PAD_GPIO_IO29__GPIO2_IO29			= IOMUX_PAD(0x234, 0x0084, 0, 0x0000, 0, 0),
+	MX93_PAD_GPIO_IO29__LPI2C3_SCL			= IOMUX_PAD(0x234, 0x0084, 1, 0x3E0, 1, 0),
+	MX93_PAD_GPIO_IO29__FLEXIO1_FLEXIO29		= IOMUX_PAD(0x234, 0x0084, 7, 0x0000, 0, 0),
+
+	MX93_PAD_CCM_CLKO1__CCMSRCGPCMIX_CLKO1		= IOMUX_PAD(0x238, 0x0088, 0, 0x0000, 0, 0),
+	MX93_PAD_CCM_CLKO1__FLEXIO1_FLEXIO26		= IOMUX_PAD(0x238, 0x0088, 4, 0x0000, 0, 0),
+	MX93_PAD_CCM_CLKO1__GPIO3_IO26			= IOMUX_PAD(0x238, 0x0088, 5, 0x0000, 0, 0),
+	MX93_PAD_CCM_CLKO2__GPIO3_IO27			= IOMUX_PAD(0x23C, 0x008C, 5, 0x0000, 0, 0),
+
+	MX93_PAD_CCM_CLKO2__CCMSRCGPCMIX_CLKO2		= IOMUX_PAD(0x23C, 0x008C, 0, 0x0000, 0, 0),
+	MX93_PAD_CCM_CLKO2__FLEXIO1_FLEXIO27		= IOMUX_PAD(0x23C, 0x008C, 4, 0x3C8, 1, 0),
+
+	MX93_PAD_CCM_CLKO3__CCMSRCGPCMIX_CLKO3		= IOMUX_PAD(0x240, 0x0090, 0, 0x0000, 0, 0),
+	MX93_PAD_CCM_CLKO3__FLEXIO2_FLEXIO28		= IOMUX_PAD(0x240, 0x0090, 4, 0x0000, 0, 0),
+	MX93_PAD_CCM_CLKO3__GPIO4_IO28			= IOMUX_PAD(0x240, 0x0090, 5, 0x0000, 0, 0),
+
+	MX93_PAD_CCM_CLKO4__CCMSRCGPCMIX_CLKO4		= IOMUX_PAD(0x244, 0x0094, 0, 0x0000, 0, 0),
+	MX93_PAD_CCM_CLKO4__FLEXIO2_FLEXIO29		= IOMUX_PAD(0x244, 0x0094, 4, 0x0000, 0, 0),
+	MX93_PAD_CCM_CLKO4__GPIO4_IO29			= IOMUX_PAD(0x244, 0x0094, 5, 0x0000, 0, 0),
+
+	MX93_PAD_ENET1_MDC__ENET_QOS_MDC		= IOMUX_PAD(0x248, 0x0098, 0, 0x0000, 0, 0),
+	MX93_PAD_ENET1_MDC__LPUART3_DCB_B		= IOMUX_PAD(0x248, 0x0098, 1, 0x0000, 0, 0),
+	MX93_PAD_ENET1_MDC__I3C2_SCL			= IOMUX_PAD(0x248, 0x0098, 2, 0x3CC, 0, 0),
+	MX93_PAD_ENET1_MDC__HSIOMIX_OTG_ID1		= IOMUX_PAD(0x248, 0x0098, 3, 0x0000, 0, 0),
+	MX93_PAD_ENET1_MDC__FLEXIO2_FLEXIO00		= IOMUX_PAD(0x248, 0x0098, 4, 0x0000, 0, 0),
+	MX93_PAD_ENET1_MDC__GPIO4_IO00			= IOMUX_PAD(0x248, 0x0098, 5, 0x0000, 0, 0),
+
+	MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO		= IOMUX_PAD(0x24C, 0x009C, 0, 0x0000, 0, 0),
+	MX93_PAD_ENET1_MDIO__LPUART3_RIN_B		= IOMUX_PAD(0x24C, 0x009C, 1, 0x0000, 0, 0),
+	MX93_PAD_ENET1_MDIO__I3C2_SDA			= IOMUX_PAD(0x24C, 0x009C, 2, 0x3D0, 0, 0),
+	MX93_PAD_ENET1_MDIO__HSIOMIX_OTG_PWR1		= IOMUX_PAD(0x24C, 0x009C, 3, 0x0000, 0, 0),
+	MX93_PAD_ENET1_MDIO__FLEXIO2_FLEXIO01		= IOMUX_PAD(0x24C, 0x009C, 4, 0x0000, 0, 0),
+	MX93_PAD_ENET1_MDIO__GPIO4_IO01			= IOMUX_PAD(0x24C, 0x009C, 5, 0x0000, 0, 0),
+
+	MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3		= IOMUX_PAD(0x250, 0x00A0, 0, 0x0000, 0, 0),
+	MX93_PAD_ENET1_TD3__CAN2_TX			= IOMUX_PAD(0x250, 0x00A0, 2, 0x0000, 0, 0),
+	MX93_PAD_ENET1_TD3__HSIOMIX_OTG_ID2		= IOMUX_PAD(0x250, 0x00A0, 3, 0x0000, 0, 0),
+	MX93_PAD_ENET1_TD3__FLEXIO2_FLEXIO02		= IOMUX_PAD(0x250, 0x00A0, 4, 0x0000, 0, 0),
+	MX93_PAD_ENET1_TD3__GPIO4_IO02			= IOMUX_PAD(0x250, 0x00A0, 5, 0x0000, 0, 0),
+
+	MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2		= IOMUX_PAD(0x254, 0x00A4, 0, 0x0000, 0, 0),
+	MX93_PAD_ENET1_TD2__CCM_ENET_QOS_CLOCK_GENERATE_REF_CLK = IOMUX_PAD(0x254, 0x00A4, 1, 0x0000, 0, 0),
+	MX93_PAD_ENET1_TD2__CAN2_RX			= IOMUX_PAD(0x254, 0x00A4, 2, 0x364, 2, 0),
+	MX93_PAD_ENET1_TD2__HSIOMIX_OTG_OC2		= IOMUX_PAD(0x254, 0x00A4, 3, 0x0000, 0, 0),
+	MX93_PAD_ENET1_TD2__FLEXIO2_FLEXIO03		= IOMUX_PAD(0x254, 0x00A4, 4, 0x0000, 0, 0),
+	MX93_PAD_ENET1_TD2__GPIO4_IO03			= IOMUX_PAD(0x254, 0x00A4, 5, 0x0000, 0, 0),
+
+	MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1		= IOMUX_PAD(0x258, 0x00A8, 0, 0x0000, 0, 0),
+	MX93_PAD_ENET1_TD1__LPUART3_RTS_B		= IOMUX_PAD(0x258, 0x00A8, 1, 0x0000, 0, 0),
+	MX93_PAD_ENET1_TD1__I3C2_PUR			= IOMUX_PAD(0x258, 0x00A8, 2, 0x0000, 0, 0),
+	MX93_PAD_ENET1_TD1__HSIOMIX_OTG_OC1		= IOMUX_PAD(0x258, 0x00A8, 3, 0x0000, 0, 0),
+	MX93_PAD_ENET1_TD1__FLEXIO2_FLEXIO04		= IOMUX_PAD(0x258, 0x00A8, 4, 0x0000, 0, 0),
+	MX93_PAD_ENET1_TD1__GPIO4_IO04			= IOMUX_PAD(0x258, 0x00A8, 5, 0x0000, 0, 0),
+	MX93_PAD_ENET1_TD1__I3C2_PUR_B			= IOMUX_PAD(0x258, 0x00A8, 6, 0x0000, 0, 0),
+
+	MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0		= IOMUX_PAD(0x25C, 0x00AC, 0, 0x0000, 0, 0),
+	MX93_PAD_ENET1_TD0__LPUART3_TX			= IOMUX_PAD(0x25C, 0x00AC, 1, 0x41C, 1, 0),
+	MX93_PAD_ENET1_TD0__FLEXIO2_FLEXIO05		= IOMUX_PAD(0x25C, 0x00AC, 4, 0x0000, 0, 0),
+	MX93_PAD_ENET1_TD0__GPIO4_IO05			= IOMUX_PAD(0x25C, 0x00AC, 5, 0x0000, 0, 0),
+
+	MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL	= IOMUX_PAD(0x260, 0x00B0, 0, 0x0000, 0, 0),
+	MX93_PAD_ENET1_TX_CTL__LPUART3_DTR_B		= IOMUX_PAD(0x260, 0x00B0, 1, 0x0000, 0, 0),
+	MX93_PAD_ENET1_TX_CTL__FLEXIO2_FLEXIO06		= IOMUX_PAD(0x260, 0x00B0, 4, 0x0000, 0, 0),
+	MX93_PAD_ENET1_TX_CTL__GPIO4_IO06		= IOMUX_PAD(0x260, 0x00B0, 5, 0x0000, 0, 0),
+
+	MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK	= IOMUX_PAD(0x264, 0x00B4, 0, 0x0000, 0, 0),
+	MX93_PAD_ENET1_TXC__ENET_QOS_TX_ER		= IOMUX_PAD(0x264, 0x00B4, 1, 0x0000, 0, 0),
+	MX93_PAD_ENET1_TXC__FLEXIO2_FLEXIO07		= IOMUX_PAD(0x264, 0x00B4, 4, 0x0000, 0, 0),
+	MX93_PAD_ENET1_TXC__GPIO4_IO07			= IOMUX_PAD(0x264, 0x00B4, 5, 0x0000, 0, 0),
+
+	MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL	= IOMUX_PAD(0x268, 0x00B8, 0, 0x0000, 0, 0),
+	MX93_PAD_ENET1_RX_CTL__LPUART3_DSR_B		= IOMUX_PAD(0x268, 0x00B8, 1, 0x0000, 0, 0),
+	MX93_PAD_ENET1_RX_CTL__HSIOMIX_OTG_PWR2		= IOMUX_PAD(0x268, 0x00B8, 3, 0x0000, 0, 0),
+	MX93_PAD_ENET1_RX_CTL__FLEXIO2_FLEXIO08		= IOMUX_PAD(0x268, 0x00B8, 4, 0x0000, 0, 0),
+	MX93_PAD_ENET1_RX_CTL__GPIO4_IO08		= IOMUX_PAD(0x268, 0x00B8, 5, 0x0000, 0, 0),
+
+	MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK	= IOMUX_PAD(0x26C, 0x00BC, 0, 0x0000, 0, 0),
+	MX93_PAD_ENET1_RXC__ENET_QOS_RX_ER		= IOMUX_PAD(0x26C, 0x00BC, 1, 0x0000, 0, 0),
+	MX93_PAD_ENET1_RXC__FLEXIO2_FLEXIO09		= IOMUX_PAD(0x26C, 0x00BC, 4, 0x0000, 0, 0),
+	MX93_PAD_ENET1_RXC__GPIO4_IO09			= IOMUX_PAD(0x26C, 0x00BC, 5, 0x0000, 0, 0),
+
+	MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0		= IOMUX_PAD(0x270, 0x00C0, 0, 0x0000, 0, 0),
+	MX93_PAD_ENET1_RD0__LPUART3_RX			= IOMUX_PAD(0x270, 0x00C0, 1, 0x418, 1, 0),
+	MX93_PAD_ENET1_RD0__FLEXIO2_FLEXIO10		= IOMUX_PAD(0x270, 0x00C0, 4, 0x0000, 0, 0),
+	MX93_PAD_ENET1_RD0__GPIO4_IO10			= IOMUX_PAD(0x270, 0x00C0, 5, 0x0000, 0, 0),
+
+	MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1		= IOMUX_PAD(0x274, 0x00C4, 0, 0x0000, 0, 0),
+	MX93_PAD_ENET1_RD1__LPUART3_CTS_B		= IOMUX_PAD(0x274, 0x00C4, 1, 0x414, 1, 0),
+	MX93_PAD_ENET1_RD1__LPTMR2_ALT1			= IOMUX_PAD(0x274, 0x00C4, 3, 0x408, 0, 0),
+	MX93_PAD_ENET1_RD1__FLEXIO2_FLEXIO11		= IOMUX_PAD(0x274, 0x00C4, 4, 0x0000, 0, 0),
+	MX93_PAD_ENET1_RD1__GPIO4_IO11			= IOMUX_PAD(0x274, 0x00C4, 5, 0x0000, 0, 0),
+
+	MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2		= IOMUX_PAD(0x278, 0x00C8, 0, 0x0000, 0, 0),
+	MX93_PAD_ENET1_RD2__LPTMR2_ALT2			= IOMUX_PAD(0x278, 0x00C8, 3, 0x40C, 0, 0),
+	MX93_PAD_ENET1_RD2__FLEXIO2_FLEXIO12		= IOMUX_PAD(0x278, 0x00C8, 4, 0x0000, 0, 0),
+	MX93_PAD_ENET1_RD2__GPIO4_IO12			= IOMUX_PAD(0x278, 0x00C8, 5, 0x0000, 0, 0),
+
+	MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3		= IOMUX_PAD(0x27C, 0x00CC, 0, 0x0000, 0, 0),
+	MX93_PAD_ENET1_RD3__FLEXSPI1_TESTER_TRIGGER	= IOMUX_PAD(0x27C, 0x00CC, 2, 0x0000, 0, 0),
+	MX93_PAD_ENET1_RD3__LPTMR2_ALT3			= IOMUX_PAD(0x27C, 0x00CC, 3, 0x410, 0, 0),
+	MX93_PAD_ENET1_RD3__FLEXIO2_FLEXIO13		= IOMUX_PAD(0x27C, 0x00CC, 4, 0x0000, 0, 0),
+	MX93_PAD_ENET1_RD3__GPIO4_IO13			= IOMUX_PAD(0x27C, 0x00CC, 5, 0x0000, 0, 0),
+
+	MX93_PAD_ENET2_MDC__ENET1_MDC			= IOMUX_PAD(0x280, 0x00D0, 0, 0x0000, 0, 0),
+	MX93_PAD_ENET2_MDC__LPUART4_DCB_B		= IOMUX_PAD(0x280, 0x00D0, 1, 0x0000, 0, 0),
+	MX93_PAD_ENET2_MDC__SAI2_RX_SYNC		= IOMUX_PAD(0x280, 0x00D0, 2, 0x0000, 0, 0),
+	MX93_PAD_ENET2_MDC__FLEXIO2_FLEXIO14		= IOMUX_PAD(0x280, 0x00D0, 4, 0x0000, 0, 0),
+	MX93_PAD_ENET2_MDC__GPIO4_IO14			= IOMUX_PAD(0x280, 0x00D0, 5, 0x0000, 0, 0),
+
+	MX93_PAD_ENET2_MDIO__ENET1_MDIO			= IOMUX_PAD(0x284, 0x00D4, 0, 0x0000, 0, 0),
+	MX93_PAD_ENET2_MDIO__LPUART4_RIN_B		= IOMUX_PAD(0x284, 0x00D4, 1, 0x0000, 0, 0),
+	MX93_PAD_ENET2_MDIO__SAI2_RX_BCLK		= IOMUX_PAD(0x284, 0x00D4, 2, 0x0000, 0, 0),
+	MX93_PAD_ENET2_MDIO__FLEXIO2_FLEXIO15		= IOMUX_PAD(0x284, 0x00D4, 4, 0x0000, 0, 0),
+	MX93_PAD_ENET2_MDIO__GPIO4_IO15			= IOMUX_PAD(0x284, 0x00D4, 5, 0x0000, 0, 0),
+	MX93_PAD_ENET2_TD3__SAI2_RX_DATA00		= IOMUX_PAD(0x288, 0x00D8, 2, 0x0000, 0, 0),
+	MX93_PAD_ENET2_TD3__FLEXIO2_FLEXIO16		= IOMUX_PAD(0x288, 0x00D8, 4, 0x0000, 0, 0),
+	MX93_PAD_ENET2_TD3__GPIO4_IO16			= IOMUX_PAD(0x288, 0x00D8, 5, 0x0000, 0, 0),
+
+	MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3		= IOMUX_PAD(0x288, 0x00D8, 0, 0x0000, 0, 0),
+
+	MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2		= IOMUX_PAD(0x28C, 0x00DC, 0, 0x0000, 0, 0),
+	MX93_PAD_ENET2_TD2__ENET1_TX_CLK		= IOMUX_PAD(0x28C, 0x00DC, 1, 0x0000, 0, 0),
+	MX93_PAD_ENET2_TD2__SAI2_RX_DATA01		= IOMUX_PAD(0x28C, 0x00DC, 2, 0x0000, 0, 0),
+	MX93_PAD_ENET2_TD2__FLEXIO2_FLEXIO17		= IOMUX_PAD(0x28C, 0x00DC, 4, 0x0000, 0, 0),
+	MX93_PAD_ENET2_TD2__GPIO4_IO17			= IOMUX_PAD(0x28C, 0x00DC, 5, 0x0000, 0, 0),
+
+	MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1		= IOMUX_PAD(0x290, 0x00E0, 0, 0x0000, 0, 0),
+	MX93_PAD_ENET2_TD1__LPUART4_RTS_B		= IOMUX_PAD(0x290, 0x00E0, 1, 0x0000, 0, 0),
+	MX93_PAD_ENET2_TD1__SAI2_RX_DATA02		= IOMUX_PAD(0x290, 0x00E0, 2, 0x0000, 0, 0),
+	MX93_PAD_ENET2_TD1__FLEXIO2_FLEXIO18		= IOMUX_PAD(0x290, 0x00E0, 4, 0x0000, 0, 0),
+	MX93_PAD_ENET2_TD1__GPIO4_IO18			= IOMUX_PAD(0x290, 0x00E0, 5, 0x0000, 0, 0),
+
+	MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0		= IOMUX_PAD(0x294, 0x00E4, 0, 0x0000, 0, 0),
+	MX93_PAD_ENET2_TD0__LPUART4_TX			= IOMUX_PAD(0x294, 0x00E4, 1, 0x428, 1, 0),
+	MX93_PAD_ENET2_TD0__SAI2_RX_DATA03		= IOMUX_PAD(0x294, 0x00E4, 2, 0x0000, 0, 0),
+	MX93_PAD_ENET2_TD0__FLEXIO2_FLEXIO19		= IOMUX_PAD(0x294, 0x00E4, 4, 0x0000, 0, 0),
+	MX93_PAD_ENET2_TD0__GPIO4_IO19			= IOMUX_PAD(0x294, 0x00E4, 5, 0x0000, 0, 0),
+
+	MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL	= IOMUX_PAD(0x298, 0x00E8, 0, 0x0000, 0, 0),
+	MX93_PAD_ENET2_TX_CTL__LPUART4_DTR_B		= IOMUX_PAD(0x298, 0x00E8, 1, 0x0000, 0, 0),
+	MX93_PAD_ENET2_TX_CTL__SAI2_TX_SYNC		= IOMUX_PAD(0x298, 0x00E8, 2, 0x0000, 0, 0),
+	MX93_PAD_ENET2_TX_CTL__FLEXIO2_FLEXIO20		= IOMUX_PAD(0x298, 0x00E8, 4, 0x0000, 0, 0),
+	MX93_PAD_ENET2_TX_CTL__GPIO4_IO20		= IOMUX_PAD(0x298, 0x00E8, 5, 0x0000, 0, 0),
+
+	MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC		= IOMUX_PAD(0x29C, 0x00EC, 0, 0x0000, 0, 0),
+	MX93_PAD_ENET2_TXC__ENET1_TX_ER			= IOMUX_PAD(0x29C, 0x00EC, 1, 0x0000, 0, 0),
+	MX93_PAD_ENET2_TXC__SAI2_TX_BCLK		= IOMUX_PAD(0x29C, 0x00EC, 2, 0x0000, 0, 0),
+	MX93_PAD_ENET2_TXC__FLEXIO2_FLEXIO21		= IOMUX_PAD(0x29C, 0x00EC, 4, 0x0000, 0, 0),
+	MX93_PAD_ENET2_TXC__GPIO4_IO21			= IOMUX_PAD(0x29C, 0x00EC, 5, 0x0000, 0, 0),
+
+	MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL	= IOMUX_PAD(0x2A0, 0x00F0, 0, 0x0000, 0, 0),
+	MX93_PAD_ENET2_RX_CTL__LPUART4_DSR_B		= IOMUX_PAD(0x2A0, 0x00F0, 1, 0x0000, 0, 0),
+	MX93_PAD_ENET2_RX_CTL__SAI2_TX_DATA00		= IOMUX_PAD(0x2A0, 0x00F0, 2, 0x0000, 0, 0),
+	MX93_PAD_ENET2_RX_CTL__FLEXIO2_FLEXIO22		= IOMUX_PAD(0x2A0, 0x00F0, 4, 0x0000, 0, 0),
+	MX93_PAD_ENET2_RX_CTL__GPIO4_IO22		= IOMUX_PAD(0x2A0, 0x00F0, 5, 0x0000, 0, 0),
+
+	MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC		= IOMUX_PAD(0x2A4, 0x00F4, 0, 0x0000, 0, 0),
+	MX93_PAD_ENET2_RXC__ENET1_RX_ER			= IOMUX_PAD(0x2A4, 0x00F4, 1, 0x0000, 0, 0),
+	MX93_PAD_ENET2_RXC__SAI2_TX_DATA01		= IOMUX_PAD(0x2A4, 0x00F4, 2, 0x0000, 0, 0),
+	MX93_PAD_ENET2_RXC__FLEXIO2_FLEXIO23		= IOMUX_PAD(0x2A4, 0x00F4, 4, 0x0000, 0, 0),
+	MX93_PAD_ENET2_RXC__GPIO4_IO23			= IOMUX_PAD(0x2A4, 0x00F4, 5, 0x0000, 0, 0),
+
+	MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0		= IOMUX_PAD(0x2A8, 0x00F8, 0, 0x0000, 0, 0),
+	MX93_PAD_ENET2_RD0__LPUART4_RX			= IOMUX_PAD(0x2A8, 0x00F8, 1, 0x424, 1, 0),
+	MX93_PAD_ENET2_RD0__SAI2_TX_DATA02		= IOMUX_PAD(0x2A8, 0x00F8, 2, 0x0000, 0, 0),
+	MX93_PAD_ENET2_RD0__FLEXIO2_FLEXIO24		= IOMUX_PAD(0x2A8, 0x00F8, 4, 0x0000, 0, 0),
+	MX93_PAD_ENET2_RD0__GPIO4_IO24			= IOMUX_PAD(0x2A8, 0x00F8, 5, 0x0000, 0, 0),
+
+	MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1		= IOMUX_PAD(0x2AC, 0x00FC, 0, 0x0000, 0, 0),
+	MX93_PAD_ENET2_RD1__SPDIF_IN			= IOMUX_PAD(0x2AC, 0x00FC, 1, 0x454, 1, 0),
+	MX93_PAD_ENET2_RD1__SAI2_TX_DATA03		= IOMUX_PAD(0x2AC, 0x00FC, 2, 0x0000, 0, 0),
+	MX93_PAD_ENET2_RD1__FLEXIO2_FLEXIO25		= IOMUX_PAD(0x2AC, 0x00FC, 4, 0x0000, 0, 0),
+	MX93_PAD_ENET2_RD1__GPIO4_IO25			= IOMUX_PAD(0x2AC, 0x00FC, 5, 0x0000, 0, 0),
+
+	MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2		= IOMUX_PAD(0x2B0, 0x100, 0, 0x0000, 0, 0),
+	MX93_PAD_ENET2_RD2__LPUART4_CTS_B		= IOMUX_PAD(0x2B0, 0x100, 1, 0x420, 1, 0),
+	MX93_PAD_ENET2_RD2__SAI2_MCLK			= IOMUX_PAD(0x2B0, 0x100, 2, 0x0000, 0, 0),
+	MX93_PAD_ENET2_RD2__MQS2_RIGHT			= IOMUX_PAD(0x2B0, 0x100, 3, 0x0000, 0, 0),
+	MX93_PAD_ENET2_RD2__FLEXIO2_FLEXIO26		= IOMUX_PAD(0x2B0, 0x100, 4, 0x0000, 0, 0),
+	MX93_PAD_ENET2_RD2__GPIO4_IO26			= IOMUX_PAD(0x2B0, 0x100, 5, 0x0000, 0, 0),
+
+	MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3		= IOMUX_PAD(0x2B4, 0x104, 0, 0x0000, 0, 0),
+	MX93_PAD_ENET2_RD3__SPDIF_OUT			= IOMUX_PAD(0x2B4, 0x104, 1, 0x0000, 0, 0),
+	MX93_PAD_ENET2_RD3__SPDIF_IN			= IOMUX_PAD(0x2B4, 0x104, 2, 0x454, 2, 0),
+	MX93_PAD_ENET2_RD3__MQS2_LEFT			= IOMUX_PAD(0x2B4, 0x104, 3, 0x0000, 0, 0),
+	MX93_PAD_ENET2_RD3__FLEXIO2_FLEXIO27		= IOMUX_PAD(0x2B4, 0x104, 4, 0x0000, 0, 0),
+	MX93_PAD_ENET2_RD3__GPIO4_IO27			= IOMUX_PAD(0x2B4, 0x104, 5, 0x0000, 0, 0),
+	MX93_PAD_SD1_CLK__FLEXIO1_FLEXIO08		= IOMUX_PAD(0x2B8, 0x108, 4, 0x38C, 1, 0),
+	MX93_PAD_SD1_CLK__GPIO3_IO08			= IOMUX_PAD(0x2B8, 0x108, 5, 0x0000, 0, 0),
+
+	MX93_PAD_SD1_CLK__USDHC1_CLK			= IOMUX_PAD(0x2B8, 0x108, 0, 0x0000, 0, 0),
+
+	MX93_PAD_SD1_CMD__USDHC1_CMD			= IOMUX_PAD(0x2BC, 0x10C, 0, 0x0000, 0, 0),
+	MX93_PAD_SD1_CMD__FLEXIO1_FLEXIO09		= IOMUX_PAD(0x2BC, 0x10C, 4, 0x390, 1, 0),
+	MX93_PAD_SD1_CMD__GPIO3_IO09			= IOMUX_PAD(0x2BC, 0x10C, 5, 0x0000, 0, 0),
+
+	MX93_PAD_SD1_DATA0__USDHC1_DATA0		= IOMUX_PAD(0x2C0, 0x110, 0, 0x0000, 0, 0),
+	MX93_PAD_SD1_DATA0__FLEXIO1_FLEXIO10		= IOMUX_PAD(0x2C0, 0x110, 4, 0x394, 1, 0),
+	MX93_PAD_SD1_DATA0__GPIO3_IO10			= IOMUX_PAD(0x2C0, 0x110, 5, 0x0000, 0, 0),
+
+	MX93_PAD_SD1_DATA1__USDHC1_DATA1		= IOMUX_PAD(0x2C4, 0x114, 0, 0x0000, 0, 0),
+	MX93_PAD_SD1_DATA1__FLEXIO1_FLEXIO11		= IOMUX_PAD(0x2C4, 0x114, 4, 0x398, 1, 0),
+	MX93_PAD_SD1_DATA1__GPIO3_IO11			= IOMUX_PAD(0x2C4, 0x114, 5, 0x0000, 0, 0),
+	MX93_PAD_SD1_DATA1__CCMSRCGPCMIX_INT_BOOT	= IOMUX_PAD(0x2C4, 0x114, 6, 0x0000, 0, 0),
+
+	MX93_PAD_SD1_DATA2__USDHC1_DATA2		= IOMUX_PAD(0x2C8, 0x118, 0, 0x0000, 0, 0),
+	MX93_PAD_SD1_DATA2__FLEXIO1_FLEXIO12		= IOMUX_PAD(0x2C8, 0x118, 4, 0x0000, 0, 0),
+	MX93_PAD_SD1_DATA2__GPIO3_IO12			= IOMUX_PAD(0x2C8, 0x118, 5, 0x0000, 0, 0),
+	MX93_PAD_SD1_DATA2__CCMSRCGPCMIX_PMIC_READY	= IOMUX_PAD(0x2C8, 0x118, 6, 0x0000, 0, 0),
+
+	MX93_PAD_SD1_DATA3__USDHC1_DATA3		= IOMUX_PAD(0x2CC, 0x11C, 0, 0x0000, 0, 0),
+	MX93_PAD_SD1_DATA3__FLEXSPI1_A_SS1_B		= IOMUX_PAD(0x2CC, 0x11C, 1, 0x0000, 0, 0),
+	MX93_PAD_SD1_DATA3__FLEXIO1_FLEXIO13		= IOMUX_PAD(0x2CC, 0x11C, 4, 0x39C, 1, 0),
+	MX93_PAD_SD1_DATA3__GPIO3_IO13			= IOMUX_PAD(0x2CC, 0x11C, 5, 0x0000, 0, 0),
+
+	MX93_PAD_SD1_DATA4__USDHC1_DATA4		= IOMUX_PAD(0x2D0, 0x120, 0, 0x0000, 0, 0),
+	MX93_PAD_SD1_DATA4__FLEXSPI1_A_DATA04		= IOMUX_PAD(0x2D0, 0x120, 1, 0x0000, 0, 0),
+	MX93_PAD_SD1_DATA4__FLEXIO1_FLEXIO14		= IOMUX_PAD(0x2D0, 0x120, 4, 0x3A0, 1, 0),
+	MX93_PAD_SD1_DATA4__GPIO3_IO14			= IOMUX_PAD(0x2D0, 0x120, 5, 0x0000, 0, 0),
+
+	MX93_PAD_SD1_DATA5__USDHC1_DATA5		= IOMUX_PAD(0x2D4, 0x124, 0, 0x0000, 0, 0),
+	MX93_PAD_SD1_DATA5__FLEXSPI1_A_DATA05		= IOMUX_PAD(0x2D4, 0x124, 1, 0x0000, 0, 0),
+	MX93_PAD_SD1_DATA5__USDHC1_RESET_B		= IOMUX_PAD(0x2D4, 0x124, 2, 0x0000, 0, 0),
+	MX93_PAD_SD1_DATA5__FLEXIO1_FLEXIO15		= IOMUX_PAD(0x2D4, 0x124, 4, 0x3A4, 1, 0),
+	MX93_PAD_SD1_DATA5__GPIO3_IO15			= IOMUX_PAD(0x2D4, 0x124, 5, 0x0000, 0, 0),
+
+	MX93_PAD_SD1_DATA6__USDHC1_DATA6		= IOMUX_PAD(0x2D8, 0x128, 0, 0x0000, 0, 0),
+	MX93_PAD_SD1_DATA6__FLEXSPI1_A_DATA06		= IOMUX_PAD(0x2D8, 0x128, 1, 0x0000, 0, 0),
+	MX93_PAD_SD1_DATA6__USDHC1_CD_B			= IOMUX_PAD(0x2D8, 0x128, 2, 0x0000, 0, 0),
+	MX93_PAD_SD1_DATA6__FLEXIO1_FLEXIO16		= IOMUX_PAD(0x2D8, 0x128, 4, 0x3A8, 1, 0),
+	MX93_PAD_SD1_DATA6__GPIO3_IO16			= IOMUX_PAD(0x2D8, 0x128, 5, 0x0000, 0, 0),
+
+	MX93_PAD_SD1_DATA7__USDHC1_DATA7		= IOMUX_PAD(0x2DC, 0x12C, 0, 0x0000, 0, 0),
+	MX93_PAD_SD1_DATA7__FLEXSPI1_A_DATA07		= IOMUX_PAD(0x2DC, 0x12C, 1, 0x0000, 0, 0),
+	MX93_PAD_SD1_DATA7__USDHC1_WP			= IOMUX_PAD(0x2DC, 0x12C, 2, 0x0000, 0, 0),
+	MX93_PAD_SD1_DATA7__FLEXIO1_FLEXIO17		= IOMUX_PAD(0x2DC, 0x12C, 4, 0x3AC, 1, 0),
+	MX93_PAD_SD1_DATA7__GPIO3_IO17			= IOMUX_PAD(0x2DC, 0x12C, 5, 0x0000, 0, 0),
+
+	MX93_PAD_SD1_STROBE__USDHC1_STROBE		= IOMUX_PAD(0x2E0, 0x130, 0, 0x0000, 0, 0),
+	MX93_PAD_SD1_STROBE__FLEXSPI1_A_DQS		= IOMUX_PAD(0x2E0, 0x130, 1, 0x0000, 0, 0),
+	MX93_PAD_SD1_STROBE__FLEXIO1_FLEXIO18		= IOMUX_PAD(0x2E0, 0x130, 4, 0x3B0, 1, 0),
+	MX93_PAD_SD1_STROBE__GPIO3_IO18			= IOMUX_PAD(0x2E0, 0x130, 5, 0x0000, 0, 0),
+
+	MX93_PAD_SD2_VSELECT__USDHC2_VSELECT		= IOMUX_PAD(0x2E4, 0x134, 0, 0x0000, 0, 0),
+	MX93_PAD_SD2_VSELECT__USDHC2_WP			= IOMUX_PAD(0x2E4, 0x134, 1, 0x0000, 0, 0),
+	MX93_PAD_SD2_VSELECT__LPTMR2_ALT3		= IOMUX_PAD(0x2E4, 0x134, 2, 0x410, 1, 0),
+	MX93_PAD_SD2_VSELECT__FLEXIO1_FLEXIO19		= IOMUX_PAD(0x2E4, 0x134, 4, 0x0000, 0, 0),
+	MX93_PAD_SD2_VSELECT__GPIO3_IO19		= IOMUX_PAD(0x2E4, 0x134, 5, 0x0000, 0, 0),
+	MX93_PAD_SD2_VSELECT__CCMSRCGPCMIX_EXT_CLK1	= IOMUX_PAD(0x2E4, 0x134, 6, 0x368, 0, 0),
+
+	MX93_PAD_SD3_CLK__USDHC3_CLK			= IOMUX_PAD(0x2E8, 0x138, 0, 0x458, 1, 0),
+	MX93_PAD_SD3_CLK__FLEXSPI1_A_SCLK		= IOMUX_PAD(0x2E8, 0x138, 1, 0x0000, 0, 0),
+	MX93_PAD_SD3_CLK__FLEXIO1_FLEXIO20		= IOMUX_PAD(0x2E8, 0x138, 4, 0x3B4, 1, 0),
+	MX93_PAD_SD3_CLK__GPIO3_IO20			= IOMUX_PAD(0x2E8, 0x138, 5, 0x0000, 0, 0),
+
+	MX93_PAD_SD3_CMD__USDHC3_CMD			= IOMUX_PAD(0x2EC, 0x13C, 0, 0x45C, 1, 0),
+	MX93_PAD_SD3_CMD__FLEXSPI1_A_SS0_B		= IOMUX_PAD(0x2EC, 0x13C, 1, 0x0000, 0, 0),
+	MX93_PAD_SD3_CMD__FLEXIO1_FLEXIO21		= IOMUX_PAD(0x2EC, 0x13C, 4, 0x0000, 0, 0),
+	MX93_PAD_SD3_CMD__GPIO3_IO21			= IOMUX_PAD(0x2EC, 0x13C, 5, 0x0000, 0, 0),
+
+	MX93_PAD_SD3_DATA0__USDHC3_DATA0		= IOMUX_PAD(0x2F0, 0x140, 0, 0x460, 1, 0),
+	MX93_PAD_SD3_DATA0__FLEXSPI1_A_DATA00		= IOMUX_PAD(0x2F0, 0x140, 1, 0x0000, 0, 0),
+	MX93_PAD_SD3_DATA0__FLEXIO1_FLEXIO22		= IOMUX_PAD(0x2F0, 0x140, 4, 0x3B8, 1, 0),
+	MX93_PAD_SD3_DATA0__GPIO3_IO22			= IOMUX_PAD(0x2F0, 0x140, 5, 0x0000, 0, 0),
+
+	MX93_PAD_SD3_DATA1__USDHC3_DATA1		= IOMUX_PAD(0x2F4, 0x144, 0, 0x464, 1, 0),
+	MX93_PAD_SD3_DATA1__FLEXSPI1_A_DATA01		= IOMUX_PAD(0x2F4, 0x144, 1, 0x0000, 0, 0),
+	MX93_PAD_SD3_DATA1__FLEXIO1_FLEXIO23		= IOMUX_PAD(0x2F4, 0x144, 4, 0x3BC, 1, 0),
+	MX93_PAD_SD3_DATA1__GPIO3_IO23			= IOMUX_PAD(0x2F4, 0x144, 5, 0x0000, 0, 0),
+
+	MX93_PAD_SD3_DATA2__USDHC3_DATA2		= IOMUX_PAD(0x2F8, 0x148, 0, 0x468, 1, 0),
+	MX93_PAD_SD3_DATA2__FLEXSPI1_A_DATA02		= IOMUX_PAD(0x2F8, 0x148, 1, 0x0000, 0, 0),
+	MX93_PAD_SD3_DATA2__FLEXIO1_FLEXIO24		= IOMUX_PAD(0x2F8, 0x148, 4, 0x3C0, 1, 0),
+	MX93_PAD_SD3_DATA2__GPIO3_IO24			= IOMUX_PAD(0x2F8, 0x148, 5, 0x0000, 0, 0),
+
+	MX93_PAD_SD3_DATA3__USDHC3_DATA3		= IOMUX_PAD(0x2FC, 0x14C, 0, 0x46C, 1, 0),
+	MX93_PAD_SD3_DATA3__FLEXSPI1_A_DATA03		= IOMUX_PAD(0x2FC, 0x14C, 1, 0x0000, 0, 0),
+	MX93_PAD_SD3_DATA3__FLEXIO1_FLEXIO25		= IOMUX_PAD(0x2FC, 0x14C, 4, 0x3C4, 1, 0),
+	MX93_PAD_SD3_DATA3__GPIO3_IO25			= IOMUX_PAD(0x2FC, 0x14C, 5, 0x0000, 0, 0),
+
+	MX93_PAD_SD2_CD_B__USDHC2_CD_B			= IOMUX_PAD(0x300, 0x150, 0, 0x0000, 0, 0),
+	MX93_PAD_SD2_CD_B__ENET_QOS_1588_EVENT0_IN	= IOMUX_PAD(0x300, 0x150, 1, 0x0000, 0, 0),
+	MX93_PAD_SD2_CD_B__I3C2_SCL			= IOMUX_PAD(0x300, 0x150, 2, 0x3CC, 1, 0),
+	MX93_PAD_SD2_CD_B__FLEXIO1_FLEXIO00		= IOMUX_PAD(0x300, 0x150, 4, 0x36C, 1, 0),
+	MX93_PAD_SD2_CD_B__GPIO3_IO00			= IOMUX_PAD(0x300, 0x150, 5, 0x0000, 0, 0),
+
+	MX93_PAD_SD2_CLK__USDHC2_CLK			= IOMUX_PAD(0x304, 0x154, 0, 0x0000, 0, 0),
+	MX93_PAD_SD2_CLK__ENET_QOS_1588_EVENT0_OUT	= IOMUX_PAD(0x304, 0x154, 1, 0x0000, 0, 0),
+	MX93_PAD_SD2_CLK__I3C2_SDA			= IOMUX_PAD(0x304, 0x154, 2, 0x3D0, 1, 0),
+	MX93_PAD_SD2_CLK__FLEXIO1_FLEXIO01		= IOMUX_PAD(0x304, 0x154, 4, 0x370, 1, 0),
+	MX93_PAD_SD2_CLK__GPIO3_IO01			= IOMUX_PAD(0x304, 0x154, 5, 0x0000, 0, 0),
+	MX93_PAD_SD2_CLK__CCMSRCGPCMIX_OBSERVE0		= IOMUX_PAD(0x304, 0x154, 6, 0x0000, 0, 0),
+
+	MX93_PAD_SD2_CMD__USDHC2_CMD			= IOMUX_PAD(0x308, 0x158, 0, 0x0000, 0, 0),
+	MX93_PAD_SD2_CMD__ENET1_1588_EVENT0_IN		= IOMUX_PAD(0x308, 0x158, 1, 0x0000, 0, 0),
+	MX93_PAD_SD2_CMD__I3C2_PUR			= IOMUX_PAD(0x308, 0x158, 2, 0x0000, 0, 0),
+	MX93_PAD_SD2_CMD__I3C2_PUR_B			= IOMUX_PAD(0x308, 0x158, 3, 0x0000, 0, 0),
+	MX93_PAD_SD2_CMD__FLEXIO1_FLEXIO02		= IOMUX_PAD(0x308, 0x158, 4, 0x374, 1, 0),
+	MX93_PAD_SD2_CMD__GPIO3_IO02			= IOMUX_PAD(0x308, 0x158, 5, 0x0000, 0, 0),
+	MX93_PAD_SD2_CMD__CCMSRCGPCMIX_OBSERVE1		= IOMUX_PAD(0x308, 0x158, 6, 0x0000, 0, 0),
+
+	MX93_PAD_SD2_DATA0__USDHC2_DATA0		= IOMUX_PAD(0x30C, 0x15C, 0, 0x0000, 0, 0),
+	MX93_PAD_SD2_DATA0__ENET1_1588_EVENT0_OUT	= IOMUX_PAD(0x30C, 0x15C, 1, 0x0000, 0, 0),
+	MX93_PAD_SD2_DATA0__CAN2_TX			= IOMUX_PAD(0x30C, 0x15C, 2, 0x0000, 0, 0),
+	MX93_PAD_SD2_DATA0__FLEXIO1_FLEXIO03		= IOMUX_PAD(0x30C, 0x15C, 4, 0x378, 1, 0),
+	MX93_PAD_SD2_DATA0__GPIO3_IO03			= IOMUX_PAD(0x30C, 0x15C, 5, 0x0000, 0, 0),
+	MX93_PAD_SD2_DATA0__CCMSRCGPCMIX_OBSERVE2	= IOMUX_PAD(0x30C, 0x15C, 6, 0x0000, 0, 0),
+
+	MX93_PAD_SD2_DATA1__USDHC2_DATA1		= IOMUX_PAD(0x310, 0x160, 0, 0x0000, 0, 0),
+	MX93_PAD_SD2_DATA1__ENET1_1588_EVENT1_IN	= IOMUX_PAD(0x310, 0x160, 1, 0x0000, 0, 0),
+	MX93_PAD_SD2_DATA1__CAN2_RX			= IOMUX_PAD(0x310, 0x160, 2, 0x364, 3, 0),
+	MX93_PAD_SD2_DATA1__FLEXIO1_FLEXIO04		= IOMUX_PAD(0x310, 0x160, 4, 0x37C, 1, 0),
+	MX93_PAD_SD2_DATA1__GPIO3_IO04			= IOMUX_PAD(0x310, 0x160, 5, 0x0000, 0, 0),
+	MX93_PAD_SD2_DATA1__CCMSRCGPCMIX_WAIT		= IOMUX_PAD(0x310, 0x160, 6, 0x0000, 0, 0),
+
+	MX93_PAD_SD2_DATA2__USDHC2_DATA2		= IOMUX_PAD(0x314, 0x164, 0, 0x0000, 0, 0),
+	MX93_PAD_SD2_DATA2__ENET1_1588_EVENT1_OUT	= IOMUX_PAD(0x314, 0x164, 1, 0x0000, 0, 0),
+	MX93_PAD_SD2_DATA2__MQS2_RIGHT			= IOMUX_PAD(0x314, 0x164, 2, 0x0000, 0, 0),
+	MX93_PAD_SD2_DATA2__FLEXIO1_FLEXIO05		= IOMUX_PAD(0x314, 0x164, 4, 0x380, 1, 0),
+	MX93_PAD_SD2_DATA2__GPIO3_IO05			= IOMUX_PAD(0x314, 0x164, 5, 0x0000, 0, 0),
+	MX93_PAD_SD2_DATA2__CCMSRCGPCMIX_STOP		= IOMUX_PAD(0x314, 0x164, 6, 0x0000, 0, 0),
+
+	MX93_PAD_SD2_DATA3__USDHC2_DATA3		= IOMUX_PAD(0x318, 0x168, 0, 0x0000, 0, 0),
+	MX93_PAD_SD2_DATA3__LPTMR2_ALT1			= IOMUX_PAD(0x318, 0x168, 1, 0x408, 1, 0),
+	MX93_PAD_SD2_DATA3__MQS2_LEFT			= IOMUX_PAD(0x318, 0x168, 2, 0x0000, 0, 0),
+	MX93_PAD_SD2_DATA3__FLEXIO1_FLEXIO06		= IOMUX_PAD(0x318, 0x168, 4, 0x384, 1, 0),
+	MX93_PAD_SD2_DATA3__GPIO3_IO06			= IOMUX_PAD(0x318, 0x168, 5, 0x0000, 0, 0),
+	MX93_PAD_SD2_DATA3__CCMSRCGPCMIX_EARLY_RESET	= IOMUX_PAD(0x318, 0x168, 6, 0x0000, 0, 0),
+
+	MX93_PAD_SD2_RESET_B__USDHC2_RESET_B		= IOMUX_PAD(0x31C, 0x16C, 0, 0x0000, 0, 0),
+	MX93_PAD_SD2_RESET_B__LPTMR2_ALT2		= IOMUX_PAD(0x31C, 0x16C, 1, 0x40C, 1, 0),
+	MX93_PAD_SD2_RESET_B__FLEXIO1_FLEXIO07		= IOMUX_PAD(0x31C, 0x16C, 4, 0x388, 1, 0),
+	MX93_PAD_SD2_RESET_B__GPIO3_IO07		= IOMUX_PAD(0x31C, 0x16C, 5, 0x0000, 0, 0),
+	MX93_PAD_SD2_RESET_B__CCMSRCGPCMIX_SYSTEM_RESET	= IOMUX_PAD(0x31C, 0x16C, 6, 0x0000, 0, 0),
+
+	MX93_PAD_I2C1_SCL__LPI2C1_SCL			= IOMUX_PAD(0x320, 0x170, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
+	MX93_PAD_I2C1_SCL__I3C1_SCL			= IOMUX_PAD(0x320, 0x170, 1, 0x0000, 0, 0),
+	MX93_PAD_I2C1_SCL__LPUART1_DCB_B		= IOMUX_PAD(0x320, 0x170, 2, 0x0000, 0, 0),
+	MX93_PAD_I2C1_SCL__TPM2_CH0			= IOMUX_PAD(0x320, 0x170, 3, 0x0000, 0, 0),
+	MX93_PAD_I2C1_SCL__GPIO1_IO00			= IOMUX_PAD(0x320, 0x170, 5, 0x0000, 0, 0),
+
+	MX93_PAD_I2C1_SDA__LPI2C1_SDA			= IOMUX_PAD(0x324, 0x174, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
+	MX93_PAD_I2C1_SDA__I3C1_SDA			= IOMUX_PAD(0x324, 0x174, 1, 0x0000, 0, 0),
+	MX93_PAD_I2C1_SDA__LPUART1_RIN_B		= IOMUX_PAD(0x324, 0x174, 2, 0x0000, 0, 0),
+	MX93_PAD_I2C1_SDA__TPM2_CH1			= IOMUX_PAD(0x324, 0x174, 3, 0x0000, 0, 0),
+	MX93_PAD_I2C1_SDA__GPIO1_IO01			= IOMUX_PAD(0x324, 0x174, 5, 0x0000, 0, 0),
+
+	MX93_PAD_I2C2_SCL__LPI2C2_SCL			= IOMUX_PAD(0x328, 0x178, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
+	MX93_PAD_I2C2_SCL__I3C1_PUR			= IOMUX_PAD(0x328, 0x178, 1, 0x0000, 0, 0),
+	MX93_PAD_I2C2_SCL__LPUART2_DCB_B		= IOMUX_PAD(0x328, 0x178, 2, 0x0000, 0, 0),
+	MX93_PAD_I2C2_SCL__TPM2_CH2			= IOMUX_PAD(0x328, 0x178, 3, 0x0000, 0, 0),
+	MX93_PAD_I2C2_SCL__SAI1_RX_SYNC			= IOMUX_PAD(0x328, 0x178, 4, 0x0000, 0, 0),
+	MX93_PAD_I2C2_SCL__GPIO1_IO02			= IOMUX_PAD(0x328, 0x178, 5, 0x0000, 0, 0),
+	MX93_PAD_I2C2_SCL__I3C1_PUR_B			= IOMUX_PAD(0x328, 0x178, 6, 0x0000, 0, 0),
+
+	MX93_PAD_I2C2_SDA__LPI2C2_SDA			= IOMUX_PAD(0x32C, 0x17C, 0 | IOMUX_CONFIG_SION, 0x0000, 0, 0),
+	MX93_PAD_I2C2_SDA__LPUART2_RIN_B		= IOMUX_PAD(0x32C, 0x17C, 2, 0x0000, 0, 0),
+	MX93_PAD_I2C2_SDA__TPM2_CH3			= IOMUX_PAD(0x32C, 0x17C, 3, 0x0000, 0, 0),
+	MX93_PAD_I2C2_SDA__SAI1_RX_BCLK			= IOMUX_PAD(0x32C, 0x17C, 4, 0x0000, 0, 0),
+	MX93_PAD_I2C2_SDA__GPIO1_IO03			= IOMUX_PAD(0x32C, 0x17C, 5, 0x0000, 0, 0),
+
+	MX93_PAD_UART1_RXD__LPUART1_RX			= IOMUX_PAD(0x330, 0x180, 0, 0x0000, 0, 0),
+	MX93_PAD_UART1_RXD__S400_UART_RX		= IOMUX_PAD(0x330, 0x180, 1, 0x0000, 0, 0),
+	MX93_PAD_UART1_RXD__LPSPI2_SIN			= IOMUX_PAD(0x330, 0x180, 2, 0x0000, 0, 0),
+	MX93_PAD_UART1_RXD__TPM1_CH0			= IOMUX_PAD(0x330, 0x180, 3, 0x0000, 0, 0),
+	MX93_PAD_UART1_RXD__GPIO1_IO04			= IOMUX_PAD(0x330, 0x180, 5, 0x0000, 0, 0),
+
+	MX93_PAD_UART1_TXD__LPUART1_TX			= IOMUX_PAD(0x334, 0x184, 0, 0x0000, 0, 0),
+	MX93_PAD_UART1_TXD__S400_UART_TX		= IOMUX_PAD(0x334, 0x184, 1, 0x0000, 0, 0),
+	MX93_PAD_UART1_TXD__LPSPI2_PCS0			= IOMUX_PAD(0x334, 0x184, 2, 0x0000, 0, 0),
+	MX93_PAD_UART1_TXD__TPM1_CH1			= IOMUX_PAD(0x334, 0x184, 3, 0x0000, 0, 0),
+	MX93_PAD_UART1_TXD__GPIO1_IO05			= IOMUX_PAD(0x334, 0x184, 5, 0x0000, 0, 0),
+
+	MX93_PAD_UART2_RXD__LPUART2_RX			= IOMUX_PAD(0x338, 0x188, 0, 0x0000, 0, 0),
+	MX93_PAD_UART2_RXD__LPUART1_CTS_B		= IOMUX_PAD(0x338, 0x188, 1, 0x0000, 0, 0),
+	MX93_PAD_UART2_RXD__LPSPI2_SOUT			= IOMUX_PAD(0x338, 0x188, 2, 0x0000, 0, 0),
+	MX93_PAD_UART2_RXD__TPM1_CH2			= IOMUX_PAD(0x338, 0x188, 3, 0x0000, 0, 0),
+	MX93_PAD_UART2_RXD__SAI1_MCLK			= IOMUX_PAD(0x338, 0x188, 4, 0x448, 0, 0),
+	MX93_PAD_UART2_RXD__GPIO1_IO06			= IOMUX_PAD(0x338, 0x188, 5, 0x0000, 0, 0),
+
+	MX93_PAD_UART2_TXD__LPUART2_TX			= IOMUX_PAD(0x33C, 0x18C, 0, 0x0000, 0, 0),
+	MX93_PAD_UART2_TXD__LPUART1_RTS_B		= IOMUX_PAD(0x33C, 0x18C, 1, 0x0000, 0, 0),
+	MX93_PAD_UART2_TXD__LPSPI2_SCK			= IOMUX_PAD(0x33C, 0x18C, 2, 0x0000, 0, 0),
+	MX93_PAD_UART2_TXD__TPM1_CH3			= IOMUX_PAD(0x33C, 0x18C, 3, 0x0000, 0, 0),
+	MX93_PAD_UART2_TXD__GPIO1_IO07			= IOMUX_PAD(0x33C, 0x18C, 5, 0x0000, 0, 0),
+
+	MX93_PAD_PDM_CLK__PDM_CLK			= IOMUX_PAD(0x340, 0x190, 0, 0x0000, 0, 0),
+	MX93_PAD_PDM_CLK__MQS1_LEFT			= IOMUX_PAD(0x340, 0x190, 1, 0x0000, 0, 0),
+	MX93_PAD_PDM_CLK__LPTMR1_ALT1			= IOMUX_PAD(0x340, 0x190, 4, 0x0000, 0, 0),
+	MX93_PAD_PDM_CLK__GPIO1_IO08			= IOMUX_PAD(0x340, 0x190, 5, 0x0000, 0, 0),
+	MX93_PAD_PDM_CLK__CAN1_TX			= IOMUX_PAD(0x340, 0x190, 6, 0x0000, 0, 0),
+
+	MX93_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM00	= IOMUX_PAD(0x344, 0x194, 0, 0x438, 2, 0),
+	MX93_PAD_PDM_BIT_STREAM0__MQS1_RIGHT		= IOMUX_PAD(0x344, 0x194, 1, 0x0000, 0, 0),
+	MX93_PAD_PDM_BIT_STREAM0__LPSPI1_PCS1		= IOMUX_PAD(0x344, 0x194, 2, 0x0000, 0, 0),
+	MX93_PAD_PDM_BIT_STREAM0__TPM1_EXTCLK		= IOMUX_PAD(0x344, 0x194, 3, 0x0000, 0, 0),
+	MX93_PAD_PDM_BIT_STREAM0__LPTMR1_ALT2		= IOMUX_PAD(0x344, 0x194, 4, 0x0000, 0, 0),
+	MX93_PAD_PDM_BIT_STREAM0__GPIO1_IO09		= IOMUX_PAD(0x344, 0x194, 5, 0x0000, 0, 0),
+	MX93_PAD_PDM_BIT_STREAM0__CAN1_RX		= IOMUX_PAD(0x344, 0x194, 6, 0x360, 0, 0),
+
+	MX93_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM01	= IOMUX_PAD(0x348, 0x198, 0, 0x43C, 2, 0),
+	MX93_PAD_PDM_BIT_STREAM1__NMI_GLUE_NMI		= IOMUX_PAD(0x348, 0x198, 1, 0x0000, 0, 0),
+	MX93_PAD_PDM_BIT_STREAM1__LPSPI2_PCS1		= IOMUX_PAD(0x348, 0x198, 2, 0x0000, 0, 0),
+	MX93_PAD_PDM_BIT_STREAM1__TPM2_EXTCLK		= IOMUX_PAD(0x348, 0x198, 3, 0x0000, 0, 0),
+	MX93_PAD_PDM_BIT_STREAM1__LPTMR1_ALT3		= IOMUX_PAD(0x348, 0x198, 4, 0x0000, 0, 0),
+	MX93_PAD_PDM_BIT_STREAM1__GPIO1_IO10		= IOMUX_PAD(0x348, 0x198, 5, 0x0000, 0, 0),
+	MX93_PAD_PDM_BIT_STREAM1__CCMSRCGPCMIX_EXT_CLK1	= IOMUX_PAD(0x348, 0x198, 6, 0x368, 1, 0),
+
+	MX93_PAD_SAI1_TXFS__SAI1_TX_SYNC		= IOMUX_PAD(0x34C, 0x19C, 0, 0x0000, 0, 0),
+	MX93_PAD_SAI1_TXFS__SAI1_TX_DATA01		= IOMUX_PAD(0x34C, 0x19C, 1, 0x0000, 0, 0),
+	MX93_PAD_SAI1_TXFS__LPSPI1_PCS0			= IOMUX_PAD(0x34C, 0x19C, 2, 0x0000, 0, 0),
+	MX93_PAD_SAI1_TXFS__LPUART2_DTR_B		= IOMUX_PAD(0x34C, 0x19C, 3, 0x0000, 0, 0),
+	MX93_PAD_SAI1_TXFS__MQS1_LEFT			= IOMUX_PAD(0x34C, 0x19C, 4, 0x0000, 0, 0),
+	MX93_PAD_SAI1_TXFS__GPIO1_IO11			= IOMUX_PAD(0x34C, 0x19C, 5, 0x0000, 0, 0),
+
+	MX93_PAD_SAI1_TXC__SAI1_TX_BCLK			= IOMUX_PAD(0x350, 0x1A0, 0, 0x0000, 0, 0),
+	MX93_PAD_SAI1_TXC__LPUART2_CTS_B		= IOMUX_PAD(0x350, 0x1A0, 1, 0x0000, 0, 0),
+	MX93_PAD_SAI1_TXC__LPSPI1_SIN			= IOMUX_PAD(0x350, 0x1A0, 2, 0x0000, 0, 0),
+	MX93_PAD_SAI1_TXC__LPUART1_DSR_B		= IOMUX_PAD(0x350, 0x1A0, 3, 0x0000, 0, 0),
+	MX93_PAD_SAI1_TXC__CAN1_RX			= IOMUX_PAD(0x350, 0x1A0, 4, 0x360, 1, 0),
+	MX93_PAD_SAI1_TXC__GPIO1_IO12			= IOMUX_PAD(0x350, 0x1A0, 5, 0x0000, 0, 0),
+
+	MX93_PAD_SAI1_TXD0__SAI1_TX_DATA00		= IOMUX_PAD(0x354, 0x1A4, 0, 0x0000, 0, 0),
+	MX93_PAD_SAI1_TXD0__LPUART2_RTS_B		= IOMUX_PAD(0x354, 0x1A4, 1, 0x0000, 0, 0),
+	MX93_PAD_SAI1_TXD0__LPSPI1_SCK			= IOMUX_PAD(0x354, 0x1A4, 2, 0x0000, 0, 0),
+	MX93_PAD_SAI1_TXD0__LPUART1_DTR_B		= IOMUX_PAD(0x354, 0x1A4, 3, 0x0000, 0, 0),
+	MX93_PAD_SAI1_TXD0__CAN1_TX			= IOMUX_PAD(0x354, 0x1A4, 4, 0x0000, 0, 0),
+	MX93_PAD_SAI1_TXD0__GPIO1_IO13			= IOMUX_PAD(0x354, 0x1A4, 5, 0x0000, 0, 0),
+
+	MX93_PAD_SAI1_RXD0__SAI1_RX_DATA00		= IOMUX_PAD(0x358, 0x1A8, 0, 0x0000, 0, 0),
+	MX93_PAD_SAI1_RXD0__SAI1_MCLK			= IOMUX_PAD(0x358, 0x1A8, 1, 0x448, 1, 0),
+	MX93_PAD_SAI1_RXD0__LPSPI1_SOUT			= IOMUX_PAD(0x358, 0x1A8, 2, 0x0000, 0, 0),
+	MX93_PAD_SAI1_RXD0__LPUART2_DSR_B		= IOMUX_PAD(0x358, 0x1A8, 3, 0x0000, 0, 0),
+	MX93_PAD_SAI1_RXD0__MQS1_RIGHT			= IOMUX_PAD(0x358, 0x1A8, 4, 0x0000, 0, 0),
+	MX93_PAD_SAI1_RXD0__GPIO1_IO14			= IOMUX_PAD(0x358, 0x1A8, 5, 0x0000, 0, 0),
+
+	MX93_PAD_WDOG_ANY__WDOG1_WDOG_ANY		= IOMUX_PAD(0x35C, 0x1AC, 0, 0x0000, 0, 0),
+	MX93_PAD_WDOG_ANY__GPIO1_IO15			= IOMUX_PAD(0x35C, 0x1AC, 5, 0x0000, 0, 0),
+};
+#endif  /* __ASM_ARCH_IMX93_PINS_H__ */
diff --git a/arch/arm/include/asm/arch-imx9/sys_proto.h b/arch/arm/include/asm/arch-imx9/sys_proto.h
new file mode 100644
index 0000000000..513aa0b958
--- /dev/null
+++ b/arch/arm/include/asm/arch-imx9/sys_proto.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2022 NXP
+ */
+
+#ifndef __ARCH_IMX9_SYS_PROTO_H
+#define __ARCH_NMX9_SYS_PROTO_H
+
+#include <asm/mach-imx/sys_proto.h>
+
+#endif
diff --git a/arch/arm/include/asm/mach-imx/iomux-v3.h b/arch/arm/include/asm/mach-imx/iomux-v3.h
index 231b9c027c..0492abd298 100644
--- a/arch/arm/include/asm/mach-imx/iomux-v3.h
+++ b/arch/arm/include/asm/mach-imx/iomux-v3.h
@@ -86,7 +86,16 @@ typedef u64 iomux_v3_cfg_t;
 #define IOMUX_CONFIG_LPSR       0x20
 #define MUX_MODE_LPSR           ((iomux_v3_cfg_t)IOMUX_CONFIG_LPSR << \
 				MUX_MODE_SHIFT)
-#ifdef CONFIG_IMX8M
+#ifdef CONFIG_IMX93
+#define PAD_CTL_FSEL2		(0x2 << 7)
+#define PAD_CTL_FSEL3		(0x3 << 7)
+#define PAD_CTL_PUE		(0x1 << 9)
+#define PAD_CTL_PDE		(0x1 << 10)
+#define PAD_CTL_ODE		(0x1 << 11)
+#define PAD_CTL_HYS		(0x1 << 12)
+#define PAD_CTL_DSE(x)		(((x) << 1) & 0x7f)
+
+#elif defined(CONFIG_IMX8M)
 #define PAD_CTL_FSEL0		(0x0 << 3)
 #define PAD_CTL_FSEL1		(0x1 << 3)
 #define PAD_CTL_FSEL2		(0x2 << 3)
diff --git a/arch/arm/include/asm/mach-imx/sys_proto.h b/arch/arm/include/asm/mach-imx/sys_proto.h
index 4b43cbccaa..c094e23d42 100644
--- a/arch/arm/include/asm/mach-imx/sys_proto.h
+++ b/arch/arm/include/asm/mach-imx/sys_proto.h
@@ -31,6 +31,7 @@ struct bd_info;
 #define is_mx7() (is_soc_type(MXC_SOC_MX7))
 #define is_imx8m() (is_soc_type(MXC_SOC_IMX8M))
 #define is_imx8() (is_soc_type(MXC_SOC_IMX8))
+#define is_imx9() (is_soc_type(MXC_SOC_IMX9))
 #define is_imxrt() (is_soc_type(MXC_SOC_IMXRT))
 
 #define is_mx6dqp() (is_cpu_type(MXC_CPU_MX6QP) || is_cpu_type(MXC_CPU_MX6DP))
@@ -81,6 +82,8 @@ struct bd_info;
 
 #define is_imx8qxp() (is_cpu_type(MXC_CPU_IMX8QXP))
 
+#define is_imx93() (is_cpu_type(MXC_CPU_IMX93))
+
 #define is_imxrt1020() (is_cpu_type(MXC_CPU_IMXRT1020))
 #define is_imxrt1050() (is_cpu_type(MXC_CPU_IMXRT1050))
 
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index 6b597520a2..b72b6af434 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -166,7 +166,7 @@ config DDRMC_VF610_CALIBRATION
 
 config IMX8_ROMAPI
 	def_bool y
-	depends on IMX8MN || IMX8MP || IMX8ULP
+	depends on IMX8MN || IMX8MP || IMX8ULP || IMX9
 
 config SPL_IMX_ROMAPI_LOADADDR
 	hex "Default load address to load image through ROM API"
diff --git a/arch/arm/mach-imx/Makefile b/arch/arm/mach-imx/Makefile
index fb463634e5..80c497e6d8 100644
--- a/arch/arm/mach-imx/Makefile
+++ b/arch/arm/mach-imx/Makefile
@@ -5,7 +5,7 @@
 #
 # (C) Copyright 2011 Freescale Semiconductor, Inc.
 
-ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6 mx7 imx8m vf610))
+ifeq ($(SOC),$(filter $(SOC),mx25 mx35 mx5 mx6 mx7 imx8m imx9 vf610))
 obj-y	= iomux-v3.o
 endif
 
@@ -29,7 +29,7 @@ endif
 obj-$(CONFIG_GPT_TIMER) += timer.o
 obj-$(CONFIG_SYS_I2C_MXC) += i2c-mxv7.o
 endif
-ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs imx8m imx8 imxrt))
+ifeq ($(SOC),$(filter $(SOC),mx7 mx6 mxs imx8m imx8 imx9 imxrt))
 obj-y	+= misc.o
 obj-$(CONFIG_CMD_PRIBLOB) += priblob.o
 obj-$(CONFIG_SPL_BUILD)	+= spl.o
@@ -195,6 +195,10 @@ flash.bin: spl/u-boot-spl.bin FORCE
 endif
 endif
 
+ifeq ($(CONFIG_ARCH_IMX9), y)
+SPL:
+endif
+
 else
 MKIMAGEFLAGS_SPL = -n $(filter-out $(PLUGIN).bin $< $(PHONY),$^) \
 		   -T $(IMAGE_TYPE) -e $(CONFIG_SPL_TEXT_BASE)
@@ -240,8 +244,8 @@ obj-$(CONFIG_ARCH_MX7ULP) += mx7ulp/
 obj-$(CONFIG_ARCH_IMX8ULP) += imx8ulp/
 obj-$(CONFIG_IMX8M) += imx8m/
 obj-$(CONFIG_ARCH_IMX8) += imx8/
+obj-$(CONFIG_ARCH_IMX9) += imx9/
 obj-$(CONFIG_ARCH_IMXRT) += imxrt/
 
-obj-$(CONFIG_IMX8MN)$(CONFIG_IMX8MP)$(CONFIG_IMX8ULP) += imx_romapi.o
 obj-$(CONFIG_SPL_BOOTROM_SUPPORT) += spl_imx_romapi.o
 obj-$(CONFIG_IMX8_ROMAPI) += romapi.o
diff --git a/arch/arm/mach-imx/imx9/Kconfig b/arch/arm/mach-imx/imx9/Kconfig
new file mode 100644
index 0000000000..ff254c2af5
--- /dev/null
+++ b/arch/arm/mach-imx/imx9/Kconfig
@@ -0,0 +1,16 @@
+if ARCH_IMX9
+
+config IMX9
+	bool
+	select HAS_CAAM
+	select ROM_UNIFIED_SECTIONS
+
+config IMX93
+	bool
+	select IMX9
+	select ARMV8_SPL_EXCEPTION_VECTORS
+
+config SYS_SOC
+	default "imx9"
+
+endif
diff --git a/arch/arm/mach-imx/imx9/Makefile b/arch/arm/mach-imx/imx9/Makefile
new file mode 100644
index 0000000000..773b12ee12
--- /dev/null
+++ b/arch/arm/mach-imx/imx9/Makefile
@@ -0,0 +1,6 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# Copyright 2022 NXP
+
+obj-y += lowlevel_init.o
+obj-y += soc.o clock.o
diff --git a/arch/arm/mach-imx/imx9/clock.c b/arch/arm/mach-imx/imx9/clock.c
new file mode 100644
index 0000000000..287e312060
--- /dev/null
+++ b/arch/arm/mach-imx/imx9/clock.c
@@ -0,0 +1,26 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 NXP
+ *
+ * Peng Fan <peng.fan@nxp.com>
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <div64.h>
+#include <errno.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <log.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+u32 get_lpuart_clk(void)
+{
+	return 24000000;
+}
diff --git a/arch/arm/mach-imx/imx9/lowlevel_init.S b/arch/arm/mach-imx/imx9/lowlevel_init.S
new file mode 100644
index 0000000000..1dc1dbfcdd
--- /dev/null
+++ b/arch/arm/mach-imx/imx9/lowlevel_init.S
@@ -0,0 +1,26 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2022 NXP
+ */
+
+#include <config.h>
+
+.align 8
+.global rom_pointer
+rom_pointer:
+	.space 256
+
+/*
+ * Routine: save_boot_params (called after reset from start.S)
+ */
+
+.global save_boot_params
+save_boot_params:
+#ifndef CONFIG_SPL_BUILD
+	/* The firmware provided ATAG/FDT address can be found in r2/x0 */
+	adr	x0, rom_pointer
+	stp	x1, x2, [x0], #16
+	stp	x3, x4, [x0], #16
+#endif
+	/* Returns */
+	b	save_boot_params_ret
diff --git a/arch/arm/mach-imx/imx9/soc.c b/arch/arm/mach-imx/imx9/soc.c
new file mode 100644
index 0000000000..d905fe76c9
--- /dev/null
+++ b/arch/arm/mach-imx/imx9/soc.c
@@ -0,0 +1,127 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2022 NXP
+ *
+ * Peng Fan <peng.fan@nxp.com>
+ */
+
+#include <common.h>
+#include <cpu_func.h>
+#include <init.h>
+#include <log.h>
+#include <asm/arch/imx-regs.h>
+#include <asm/global_data.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/sys_proto.h>
+#include <asm/mach-imx/boot_mode.h>
+#include <asm/mach-imx/syscounter.h>
+#include <asm/armv8/mmu.h>
+#include <dm/uclass.h>
+#include <env.h>
+#include <env_internal.h>
+#include <errno.h>
+#include <fdt_support.h>
+#include <linux/bitops.h>
+#include <asm/setup.h>
+#include <asm/bootm.h>
+#include <asm/arch-imx/cpu.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+u32 get_cpu_rev(void)
+{
+	return (MXC_CPU_IMX93 << 12) | CHIP_REV_1_0;
+}
+
+static struct mm_region imx93_mem_map[] = {
+	{
+		/* ROM */
+		.virt = 0x0UL,
+		.phys = 0x0UL,
+		.size = 0x100000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_OUTER_SHARE
+	}, {
+		/* OCRAM */
+		.virt = 0x20480000UL,
+		.phys = 0x20480000UL,
+		.size = 0xA0000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_OUTER_SHARE
+	}, {
+		/* AIPS */
+		.virt = 0x40000000UL,
+		.phys = 0x40000000UL,
+		.size = 0x40000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		/* Flexible Serial Peripheral Interface */
+		.virt = 0x28000000UL,
+		.phys = 0x28000000UL,
+		.size = 0x30000000UL,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+			 PTE_BLOCK_NON_SHARE |
+			 PTE_BLOCK_PXN | PTE_BLOCK_UXN
+	}, {
+		/* DRAM1 */
+		.virt = 0x80000000UL,
+		.phys = 0x80000000UL,
+		.size = PHYS_SDRAM_SIZE,
+		.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+			 PTE_BLOCK_OUTER_SHARE
+	}, {
+		/* empty entrie to split table entry 5 if needed when TEEs are used */
+		0,
+	}, {
+		/* List terminator */
+		0,
+	}
+};
+
+struct mm_region *mem_map = imx93_mem_map;
+
+int dram_init(void)
+{
+	gd->ram_size = PHYS_SDRAM_SIZE;
+
+	return 0;
+}
+
+void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
+{
+	mac[0] = 0x1;
+	mac[1] = 0x2;
+	mac[2] = 0x3;
+	mac[3] = 0x4;
+	mac[4] = 0x5;
+	mac[5] = 0x6;
+}
+
+int print_cpuinfo(void)
+{
+	u32 cpurev;
+
+	cpurev = get_cpu_rev();
+
+	printf("CPU:   i.MX93 rev%d.%d\n", (cpurev & 0x000F0) >> 4, (cpurev & 0x0000F) >> 0);
+
+	return 0;
+}
+
+int arch_misc_init(void)
+{
+	return 0;
+}
+
+int ft_system_setup(void *blob, struct bd_info *bd)
+{
+	return 0;
+}
+
+int arch_cpu_init(void)
+{
+	return 0;
+}
diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c
index e5ad993b8d..ef00969a5e 100644
--- a/arch/arm/mach-imx/spl.c
+++ b/arch/arm/mach-imx/spl.c
@@ -147,7 +147,7 @@ u32 spl_boot_device(void)
 	return BOOT_DEVICE_NONE;
 }
 
-#elif defined(CONFIG_MX7) || defined(CONFIG_IMX8M) || defined(CONFIG_IMX8)
+#elif defined(CONFIG_MX7) || defined(CONFIG_IMX8M) || defined(CONFIG_IMX8) || defined(CONFIG_IMX9)
 /* Translate iMX7/i.MX8M boot device to the SPL boot device enumeration */
 u32 spl_boot_device(void)
 {