From: Ye Li <ye.li@nxp.com>
Date: Thu, 15 Jun 2023 10:09:13 +0000 (+0800)
Subject: imx: misc: ele_mu: Update ELE MU driver
X-Git-Url: http://git.dujemihanovic.xyz/login.html?a=commitdiff_plain;h=78b4cf75307f4704881b7b7501721f27f2691f9f;p=u-boot.git

imx: misc: ele_mu: Update ELE MU driver

Extend the RX timeout value to 10s, because when authentication is failed
the ELE needs long time (>2s for 28M image) to return the result. Print
rx wait info per 1s.

Also correct TX and RX status registers in debug.

Signed-off-by: Ye Li <ye.li@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
---

diff --git a/drivers/misc/imx_ele/ele_mu.c b/drivers/misc/imx_ele/ele_mu.c
index 956f8a1eb2..053cdcf0fe 100644
--- a/drivers/misc/imx_ele/ele_mu.c
+++ b/drivers/misc/imx_ele/ele_mu.c
@@ -42,7 +42,7 @@ int mu_hal_sendmsg(ulong base, u32 reg_index, u32 msg)
 
 	assert(reg_index < MU_TR_COUNT);
 
-	debug("sendmsg sr 0x%x\n", readl(&mu_base->sr));
+	debug("sendmsg tsr 0x%x\n", readl(&mu_base->tsr));
 
 	/* Wait TX register to be empty. */
 	ret = readl_poll_timeout(&mu_base->tsr, val, val & mask, 10000);
@@ -64,14 +64,24 @@ int mu_hal_receivemsg(ulong base, u32 reg_index, u32 *msg)
 	u32 mask = MU_SR_RF0_MASK << reg_index;
 	u32 val;
 	int ret;
+	u32 count = 10;
 
 	assert(reg_index < MU_RR_COUNT);
 
-	debug("receivemsg sr 0x%x\n", readl(&mu_base->sr));
+	debug("receivemsg rsr 0x%x\n", readl(&mu_base->rsr));
 
-	/* Wait RX register to be full. */
-	ret = readl_poll_timeout(&mu_base->rsr, val, val & mask, 10000);
-	if (ret < 0) {
+	do {
+		/* Wait RX register to be full. */
+		ret = readl_poll_timeout(&mu_base->rsr, val, val & mask, 1000000);
+		if (ret < 0) {
+			count--;
+			printf("mu receive msg wait %us\n", 10 - count);
+		} else {
+			break;
+		}
+	} while (count > 0);
+
+	if (count == 0) {
 		debug("%s timeout\n", __func__);
 		return -ETIMEDOUT;
 	}