From: Marek Vasut <marek.vasut+renesas@gmail.com>
Date: Tue, 27 Apr 2021 17:52:53 +0000 (+0200)
Subject: clk: renesas: Handle R8A779A0 V3U clock types in Gen3 clock code
X-Git-Url: http://git.dujemihanovic.xyz/login.html?a=commitdiff_plain;h=44c78aa7ac0f4b22491350278f0dd77585416248;p=u-boot.git

clk: renesas: Handle R8A779A0 V3U clock types in Gen3 clock code

On R8A779A0 V3U SoC, PLL1 and PLL5 use a divider value
from cpg_pll_configs table while PLL{20,21,30,31,4} use
different control offset. Introduce new types to handle
this and handle those types in the Gen3 clock code.

Based on "clk: renesas: Add support for R8A779A0 V3U PLLn"
by Hai Pham <hai.pham.ud@renesas.com>

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
---

diff --git a/drivers/clk/renesas/clk-rcar-gen3.c b/drivers/clk/renesas/clk-rcar-gen3.c
index 7b42e28e83..c7dba341c1 100644
--- a/drivers/clk/renesas/clk-rcar-gen3.c
+++ b/drivers/clk/renesas/clk-rcar-gen3.c
@@ -253,6 +253,28 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
 		return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
 						CPG_PLL4CR, 0, 0, "PLL4");
 
+	case CLK_TYPE_R8A779A0_MAIN:
+		return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
+						0, 1, pll_config->extal_div,
+						"V3U_MAIN");
+
+	case CLK_TYPE_R8A779A0_PLL1:
+		return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
+						0, pll_config->pll1_mult,
+						pll_config->pll1_div,
+						"V3U_PLL1");
+
+	case CLK_TYPE_R8A779A0_PLL2X_3X:
+		return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
+						core->offset, 0, 0,
+						"V3U_PLL2X_3X");
+
+	case CLK_TYPE_R8A779A0_PLL5:
+		return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
+						0, pll_config->pll5_mult,
+						pll_config->pll5_div,
+						"V3U_PLL5");
+
 	case CLK_TYPE_FF:
 		return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
 						0, core->mult, core->div,
@@ -268,6 +290,8 @@ static u64 gen3_clk_get_rate64(struct clk *clk)
 		return rate;
 
 	case CLK_TYPE_GEN3_SD:		/* FIXME */
+		fallthrough;
+	case CLK_TYPE_R8A779A0_SD:
 		value = readl(priv->base + core->offset);
 		value &= CPG_SD_STP_MASK | CPG_SD_FC_MASK;
 
diff --git a/drivers/clk/renesas/rcar-gen3-cpg.h b/drivers/clk/renesas/rcar-gen3-cpg.h
index 4fce0a9946..aa940a1ca2 100644
--- a/drivers/clk/renesas/rcar-gen3-cpg.h
+++ b/drivers/clk/renesas/rcar-gen3-cpg.h
@@ -27,6 +27,13 @@ enum rcar_gen3_clk_types {
 	CLK_TYPE_GEN3_E3_RPCSRC,
 	CLK_TYPE_GEN3_RPC,
 	CLK_TYPE_GEN3_RPCD2,
+	CLK_TYPE_R8A779A0_MAIN,
+	CLK_TYPE_R8A779A0_PLL1,
+	CLK_TYPE_R8A779A0_PLL2X_3X,	/* PLL[23][01] */
+	CLK_TYPE_R8A779A0_PLL5,
+	CLK_TYPE_R8A779A0_SD,
+	CLK_TYPE_R8A779A0_MDSEL,	/* Select parent/divider using mode pin */
+	CLK_TYPE_R8A779A0_OSC,	/* OSC EXTAL predivider and fixed divider */
 
 	/* SoC specific definitions start here */
 	CLK_TYPE_GEN3_SOC_BASE,
@@ -69,6 +76,8 @@ struct rcar_gen3_cpg_pll_config {
 	u8 pll3_mult;
 	u8 pll3_div;
 	u8 osc_prediv;
+	u8 pll5_mult;
+	u8 pll5_div;
 };
 
 #define CPG_RST_MODEMR	0x060