From: Pali Rohár Date: Fri, 24 Sep 2021 20:59:18 +0000 (+0200) Subject: arm: mvebu: a38x: serdes: Don't set PCIe Common Clock Configuration X-Git-Url: http://git.dujemihanovic.xyz/login.html?a=commitdiff_plain;h=3fc8b90d68e1524275a126d659dc31d8b1246772;p=u-boot.git arm: mvebu: a38x: serdes: Don't set PCIe Common Clock Configuration Enabling Common Clock Configuration bit in PCIe Root Port Link Control Register should not be done unconditionally. It is enabled by operating system as part of ASPM. Also after enabling Common Clock Configuration it is required to do more work, like retraining link. Some cards may be broken due to this incomplete Common Clock Configuration and some cards are broken and do not support ASPM at all. Remove this incomplete code for Common Clock Configuration. It really should not be done in SerDes code as it is not related to SerDes, but to PCIe subsystem. Signed-off-by: Pali Rohár Reviewed-by: Marek Behún Reviewed-by: Stefan Roese --- diff --git a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c index c089479a9b..d2bc3ab25c 100644 --- a/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c +++ b/arch/arm/mach-mvebu/serdes/a38x/high_speed_env_spec.c @@ -1735,21 +1735,6 @@ int serdes_power_up_ctrl(u32 serdes_num, int serdes_power_up, reg_data |= (is_pex_by1 ? 1 : 4) << 4; reg_write(PEX0_RP_PCIE_CFG_OFFSET + PCI_EXP_LNKCAP, reg_data); - - /* - * Set Common Clock Configuration to indicates - * that both devices on the link use a - * distributed common reference clock. - */ - reg_data = reg_read(PEX_CFG_DIRECT_ACCESS( - pex_idx, - PEX_LINK_CTRL_STAT_REG)); - reg_data &= ~0x40; - reg_data |= 0x40; - reg_write(PEX_CFG_DIRECT_ACCESS( - pex_idx, - PEX_LINK_CTRL_STAT_REG), - reg_data); } CHECK_STATUS(mv_seq_exec(serdes_num, PEX_POWER_UP_SEQ));