From: Marek Vasut <marek.vasut+renesas@gmail.com>
Date: Wed, 13 Jun 2018 06:02:55 +0000 (+0200)
Subject: pinctrl: renesas: Fix DRV register offset
X-Git-Tag: v2025.01-rc5-pxa1908~3300^2~11
X-Git-Url: http://git.dujemihanovic.xyz/login.html?a=commitdiff_plain;h=0ff9e4800f21e4250ac8a6ca908de00851f896d8;p=u-boot.git

pinctrl: renesas: Fix DRV register offset

Use fixed 4bit size for generating the DRV register element mask,
not the size of the value, which can be smaller.

Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com>
Cc: Masahiro Yamada <yamada.masahiro@socionext.com>
Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
---

diff --git a/drivers/pinctrl/renesas/pfc.c b/drivers/pinctrl/renesas/pfc.c
index 90011537a8..b3a4ff9049 100644
--- a/drivers/pinctrl/renesas/pfc.c
+++ b/drivers/pinctrl/renesas/pfc.c
@@ -591,7 +591,7 @@ static int sh_pfc_pinconf_set_drive_strength(struct sh_pfc *pfc,
 	strength = strength / step - 1;
 
 	val = sh_pfc_read_raw_reg(reg, 32);
-	val &= ~GENMASK(offset + size - 1, offset);
+	val &= ~GENMASK(offset + 4 - 1, offset);
 	val |= strength << offset;
 
 	if (unlock_reg)