--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __ASM_ARCH_BOOT0_H__
+#define __ASM_ARCH_BOOT0_H__
+
+#include <asm/arch-rockchip/boot0.h>
+
+#endif
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ */
+
+#ifndef __ASM_ARCH_GPIO_H__
+#define __ASM_ARCH_GPIO_H__
+
+#include <asm/arch-rockchip/gpio.h>
+
+#endif
The Rockchip RV1108 is a ARM-based SoC with a single-core Cortex-A7
and a DSP.
+config ROCKCHIP_RV1126
+ bool "Support Rockchip RV1126"
+ select CPU_V7A
+ select SKIP_LOWLEVEL_INIT_ONLY
+ select TPL
+ select SUPPORT_TPL
+ select TPL_NEEDS_SEPARATE_STACK
+ select TPL_ROCKCHIP_BACK_TO_BROM
+ select SPL
+ select SUPPORT_SPL
+ select SPL_STACK_R
+ select CLK
+ select FIT
+ select PINCTRL
+ select RAM
+ select ROCKCHIP_SDRAM_COMMON
+ select REGMAP
+ select SYSCON
+ select DM_PMIC
+ select DM_REGULATOR_FIXED
+ select DM_RESET
+ select REGULATOR_RK8XX
+ select PMIC_RK8XX
+ select BOARD_LATE_INIT
+ imply ROCKCHIP_COMMON_BOARD
+ imply TPL_DM
+ imply TPL_LIBCOMMON_SUPPORT
+ imply TPL_LIBGENERIC_SUPPORT
+ imply TPL_OF_CONTROL
+ imply TPL_OF_PLATDATA
+ imply TPL_RAM
+ imply TPL_ROCKCHIP_COMMON_BOARD
+ imply TPL_SERIAL
+ imply SPL_CLK
+ imply SPL_DM
+ imply SPL_DRIVERS_MISC
+ imply SPL_LIBCOMMON_SUPPORT
+ imply SPL_LIBGENERIC_SUPPORT
+ imply SPL_OF_CONTROL
+ imply SPL_RAM
+ imply SPL_REGMAP
+ imply SPL_ROCKCHIP_COMMON_BOARD
+ imply SPL_SERIAL
+ imply SPL_SYSCON
+
config ROCKCHIP_USB_UART
bool "Route uart output to usb pins"
help
source "arch/arm/mach-rockchip/rk3399/Kconfig"
source "arch/arm/mach-rockchip/rk3568/Kconfig"
source "arch/arm/mach-rockchip/rv1108/Kconfig"
+source "arch/arm/mach-rockchip/rv1126/Kconfig"
endif
obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399/
obj-$(CONFIG_ROCKCHIP_RK3568) += rk3568/
obj-$(CONFIG_ROCKCHIP_RV1108) += rv1108/
+obj-$(CONFIG_ROCKCHIP_RV1126) += rv1126/
# Clear out SPL objects, in case this is a TPL build
obj-spl-$(CONFIG_TPL_BUILD) =
--- /dev/null
+if ROCKCHIP_RV1126
+
+config SOC_SPECIFIC_OPTIONS # dummy
+ def_bool y
+ select HAS_CUSTOM_SYS_INIT_SP_ADDR
+
+config ROCKCHIP_BOOT_MODE_REG
+ default 0xfe020200
+
+config ROCKCHIP_STIMER_BASE
+ default 0xff670020
+
+config SYS_SOC
+ default "rv1126"
+
+config CUSTOM_SYS_INIT_SP_ADDR
+ default 0x800000
+
+config SPL_STACK
+ default 0x600000
+
+config SPL_STACK_R_ADDR
+ default 0x800000
+
+config TPL_LDSCRIPT
+ default "arch/arm/mach-rockchip/u-boot-tpl.lds"
+
+config TPL_STACK
+ default 0xff718000
+
+config TPL_SYS_MALLOC_F_LEN
+ default 0x2000
+
+config TPL_TEXT_BASE
+ default 0xff701000
+
+config SYS_MALLOC_F_LEN
+ default 0x2000
+
+config TEXT_BASE
+ default 0x600000
+
+endif
--- /dev/null
+#
+# (C) Copyright 2019 Rockchip Electronics Co., Ltd
+# Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
+#
+# SPDX-License-Identifier: GPL-2.0+
+#
+
+obj-y += rv1126.o
+
+ifndef CONFIG_TPL_BUILD
+obj-y += clk_rv1126.o
+obj-y += syscon_rv1126.o
+endif
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
+ * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <syscon.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/cru_rv1126.h>
+#include <linux/err.h>
+
+int rockchip_get_clk(struct udevice **devp)
+{
+ return uclass_get_device_by_driver(UCLASS_CLK,
+ DM_DRIVER_GET(rockchip_rv1126_cru), devp);
+}
+
+void *rockchip_get_cru(void)
+{
+ struct rv1126_clk_priv *priv;
+ struct udevice *dev;
+ int ret;
+
+ ret = rockchip_get_clk(&dev);
+ if (ret)
+ return ERR_PTR(ret);
+
+ priv = dev_get_priv(dev);
+
+ return priv->cru;
+}
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2019 Rockchip Electronics Co., Ltd
+ * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <asm/arch-rockchip/bootrom.h>
+#include <asm/arch-rockchip/hardware.h>
+#include <asm/arch-rockchip/grf_rv1126.h>
+
+#define GRF_BASE 0xFE000000
+
+const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = {
+ [BROM_BOOTSOURCE_EMMC] = "/mmc@ffc50000",
+ [BROM_BOOTSOURCE_SD] = "/mmc@ffc60000",
+};
+
+/* GRF_GPIO3A_IOMUX_L */
+enum {
+ GPIO3A3_SHIFT = 12,
+ GPIO3A3_MASK = GENMASK(14, 12),
+ GPIO3A3_GPIO = 0,
+ GPIO3A3_UART2_RX_M1,
+ GPIO3A3_A7_JTAG_TMS_M1,
+
+ GPIO3A2_SHIFT = 8,
+ GPIO3A2_MASK = GENMASK(10, 8),
+ GPIO3A2_GPIO = 0,
+ GPIO3A2_UART2_TX_M1,
+ GPIO3A2_A7_JTAG_TCK_M1,
+};
+
+/* GRF_IOFUNC_CON2 */
+enum {
+ UART2_IO_SEL_SHIFT = 8,
+ UART2_IO_SEL_MASK = GENMASK(8, 8),
+ UART2_IO_SEL_M0 = 0,
+ UART2_IO_SEL_M1,
+};
+
+void board_debug_uart_init(void)
+{
+ static struct rv1126_grf * const grf = (void *)GRF_BASE;
+
+ /* Enable early UART2 channel m1 on the rv1126 */
+ rk_clrsetreg(&grf->iofunc_con2, UART2_IO_SEL_MASK,
+ UART2_IO_SEL_M1 << UART2_IO_SEL_SHIFT);
+
+ /* Switch iomux */
+ rk_clrsetreg(&grf->gpio3a_iomux_l,
+ GPIO3A3_MASK | GPIO3A2_MASK,
+ GPIO3A3_UART2_RX_M1 << GPIO3A3_SHIFT |
+ GPIO3A2_UART2_TX_M1 << GPIO3A2_SHIFT);
+}
+
+#ifndef CONFIG_TPL_BUILD
+int arch_cpu_init(void)
+{
+ return 0;
+}
+#endif
--- /dev/null
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <log.h>
+#include <syscon.h>
+#include <asm/arch-rockchip/clock.h>
+
+static const struct udevice_id rv1126_syscon_ids[] = {
+ { .compatible = "rockchip,rv1126-grf", .data = ROCKCHIP_SYSCON_GRF },
+ { .compatible = "rockchip,rv1126-pmugrf", .data = ROCKCHIP_SYSCON_PMUGRF },
+ { }
+};
+
+U_BOOT_DRIVER(syscon_rv1126) = {
+ .name = "rv1126_syscon",
+ .id = UCLASS_SYSCON,
+ .of_match = rv1126_syscon_ids,
+};
+
+#if CONFIG_IS_ENABLED(OF_PLATDATA)
+static int rv1126_syscon_bind_of_plat(struct udevice *dev)
+{
+ dev->driver_data = dev->driver->of_match->data;
+ debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data);
+
+ return 0;
+}
+
+U_BOOT_DRIVER(rockchip_rv1126_pmu) = {
+ .name = "rockchip_rv1126_pmu",
+ .id = UCLASS_SYSCON,
+ .of_match = rv1126_syscon_ids,
+ .bind = rv1126_syscon_bind_of_plat,
+};
+
+U_BOOT_DRIVER(rockchip_rv1126_pmugrf) = {
+ .name = "rockchip_rv1126_pmugrf",
+ .id = UCLASS_SYSCON,
+ .of_match = rv1126_syscon_ids + 1,
+ .bind = rv1126_syscon_bind_of_plat,
+};
+#endif
config TPL_MAX_SIZE
hex "Maximum size (in bytes) for the TPL stage"
default 0x2e000 if ROCKCHIP_RK3399
- default 0x8000 if ROCKCHIP_RK3288
+ default 0x8000 if ROCKCHIP_RK3288 || ROCKCHIP_RV1126
default 0x7000 if ROCKCHIP_RK322X || ROCKCHIP_RK3328 || ROCKCHIP_RK3368
default 0x2800 if ROCKCHIP_PX30
default 0x0
--- /dev/null
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * (C) Copyright 2019 Rockchip Electronics Co., Ltd
+ * Copyright (c) 2022 Edgeble AI Technologies Pvt. Ltd.
+ */
+
+#ifndef __CONFIG_RV1126_COMMON_H
+#define __CONFIG_RV1126_COMMON_H
+
+#include "rockchip-common.h"
+
+#define CFG_SYS_HZ_CLOCK 24000000
+
+#define CFG_IRAM_BASE 0xff700000
+
+#define GICD_BASE 0xfeff1000
+#define GICC_BASE 0xfeff2000
+
+#define CFG_SYS_SDRAM_BASE 0
+#define SDRAM_MAX_SIZE 0xfd000000
+
+/* memory size > 128MB */
+#define ENV_MEM_LAYOUT_SETTINGS \
+ "scriptaddr=0x00000000\0" \
+ "pxefile_addr_r=0x00100000\0" \
+ "fdt_addr_r=0x08300000\0" \
+ "kernel_addr_r=0x02008000\0" \
+ "ramdisk_addr_r=0x0a200000\0"
+
+#include <config_distro_bootcmd.h>
+#define CFG_EXTRA_ENV_SETTINGS \
+ "fdt_high=0x0fffffff\0" \
+ "initrd_high=0x0fffffff\0" \
+ "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
+ "partitions=" PARTS_DEFAULT \
+ ENV_MEM_LAYOUT_SETTINGS \
+ ROCKCHIP_DEVICE_SETTINGS \
+ BOOTENV
+
+#endif /* __CONFIG_RV1126_COMMON_H */
projects / u-boot.git / commitdiff