ppc4xx: Enable booting with Option E on 460EX/EXr/GT

This patch enables booting with option E on the PPC460EX/EXr/GT.
When booting with Option E, the PLL is in bypass, CPR0_PLLC[ENG]=0.
The Software Boot Configuration Procedure is needed to engage the
PLL and perform a chip reset.

Signed-off-by: Stefan Roese <sr@denx.de>

diff --git a/arch/powerpc/cpu/ppc4xx/cpu_init.c b/arch/powerpc/cpu/ppc4xx/cpu_init.c
index 8a6e545c1aba8987fc3c651d7cfd22b8408108e2..c04eede90da87385000f622e68887ae451d8640d 100644 (file)
--- a/arch/powerpc/cpu/ppc4xx/cpu_init.c
+++ b/arch/powerpc/cpu/ppc4xx/cpu_init.c
@@ -36,6 +36,26 @@ DECLARE_GLOBAL_DATA_PTR;
 #define CONFIG_SYS_PLL_RECONFIG        0
 #endif
 
+#if defined(CONFIG_440EPX) || \
+    defined(CONFIG_460EX) || defined(CONFIG_460GT)
+static void reset_with_rli(void)
+{
+       u32 reg;
+
+       /*
+        * Set reload inhibit so configuration will persist across
+        * processor resets
+        */
+       mfcpr(CPR0_ICFG, reg);
+       reg |= CPR0_ICFG_RLI_MASK;
+       mtcpr(CPR0_ICFG, reg);
+
+       /* Reset processor if configuration changed */
+       __asm__ __volatile__ ("sync; isync");
+       mtspr(SPRN_DBCR0, 0x20000000);
+}
+#endif
+
 void reconfigure_pll(u32 new_cpu_freq)
 {
 #if defined(CONFIG_440EPX)
@@ -166,19 +186,28 @@ void reconfigure_pll(u32 new_cpu_freq)
                }
        }
 
-       if (reset_needed) {
+       /* Now reset the CPU if needed */
+       if (reset_needed)
+               reset_with_rli();
+#endif
+
+#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
+       u32 reg;
+
+       /*
+        * See "9.2.1.1 Booting with Option E" in the 460EX/GT
+        * users manual
+        */
+       mfcpr(CPR0_PLLC, reg);
+       if ((reg & (CPR0_PLLC_RST | CPR0_PLLC_ENG)) == CPR0_PLLC_RST) {
                /*
-                * Set reload inhibit so configuration will persist across
-                * processor resets
+                * Set engage bit
                 */
-               mfcpr(CPR0_ICFG, reg);
-               reg &= ~CPR0_ICFG_RLI_MASK;
-               reg |= 1 << 31;
-               mtcpr(CPR0_ICFG, reg);
+               reg = (reg & ~CPR0_PLLC_RST) | CPR0_PLLC_ENG;
+               mtcpr(CPR0_PLLC, reg);
 
-               /* Reset processor if configuration changed */
-               __asm__ __volatile__ ("sync; isync");
-               mtspr(SPRN_DBCR0, 0x20000000);
+               /* Now reset the CPU */
+               reset_with_rli();
        }
 #endif
 }

diff --git a/include/ppc440.h b/include/ppc440.h
index 5f87d2c600e04bc649b5e1d29c20dad597f8b407..c807dda2ae768117970d47e19212fce89b9b6684 100644 (file)
--- a/include/ppc440.h
+++ b/include/ppc440.h
@@ -1719,6 +1719,13 @@
 #define CPR0_PERD_PERDV0_MASK  0x07000000
 #endif
 
+#if defined(CONFIG_460EX) || defined(CONFIG_460GT)
+#define CPR0_ICFG_RLI_MASK     0x80000000
+
+#define CPR0_PLLC_RST          0x80000000
+#define CPR0_PLLC_ENG          0x40000000
+#endif
+
 /*-----------------------------------------------------------------------------
 | PCI Internal Registers et. al. (accessed via plb)
 +----------------------------------------------------------------------------*/