]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
powerpc: dts: p2020: Define L2 cache node
authorPali Rohár <pali@kernel.org>
Fri, 8 Apr 2022 12:39:57 +0000 (14:39 +0200)
committerPriyanka Jain <priyanka.jain@nxp.com>
Tue, 26 Apr 2022 11:48:39 +0000 (17:18 +0530)
Copy definition of L2 cache node from upstream Linux kernel P2020 dts files.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
arch/powerpc/dts/p2020-post.dtsi
arch/powerpc/dts/p2020.dtsi

index 0a296cffe56f04d9ac67cb10e5682063358ec400..1c3f78798eff87d560036e0f9c93d61dd521eb25 100644 (file)
 /include/ "pq3-duart-0.dtsi"
 /include/ "pq3-gpio-0.dtsi"
 
+       L2: l2-cache-controller@20000 {
+               compatible = "fsl,p2020-l2-cache-controller";
+               reg = <0x20000 0x1000>;
+               cache-line-size = <32>; /* 32 bytes */
+               cache-size = <0x80000>; /* L2,512K */
+               interrupts = <16 2 0 0>;
+       };
+
 /include/ "pq3-etsec1-0.dtsi"
 /include/ "pq3-etsec1-timer-0.dtsi"
 
index 7c4c2061d4c33991cc3f5f2aa4bd97c84d22b4ef..7fdcb85c80948049e9ca409ffe2cc3bb9b2f0c1d 100644 (file)
                cpu0: PowerPC,P2020@0 {
                        device_type = "cpu";
                        reg = <0>;
+                       next-level-cache = <&L2>;
                };
                cpu1: PowerPC,P2020@1 {
                        device_type = "cpu";
                        reg = <1>;
+                       next-level-cache = <&L2>;
                };
        };
 };