]> git.dujemihanovic.xyz Git - u-boot.git/commitdiff
rockchip: rk3399: Include uart related pinctrl nodes in TPL/SPL
authorJonas Karlman <jonas@kwiboo.se>
Tue, 30 Apr 2024 15:30:23 +0000 (15:30 +0000)
committerKever Yang <kever.yang@rock-chips.com>
Tue, 7 May 2024 07:56:08 +0000 (15:56 +0800)
The initial serial console UART iomux is typically configured in
board_debug_uart_init() at TPL stage on Rockchip platform.

Later stages typically use pinctrl driver to configure iomux UART once
again based on the control FDT.

Include uart related pinctrl nodes in TPL/SPL control FDT to make it
possible for pinctrl driver to configure UART iomux at TPL/SPL stage.

Following debug log message may also be seen at U-Boot pre-reloc stage:

  ns16550_serial serial@ff1a0000: pinctrl_select_state_full: uclass_get_device_by_phandle_id: err=-19

This can be resolved by including bootph prop for U-Bood pre-reloc
phase (bootph-some-ram or bootph-all). However, this has intentionally
been excluded due to including it unnecessarily slows down boot around
200-400 ms.

Also add the clock-frequency prop similar to what has been done for
other Rockchip SoCs.

Signed-off-by: Jonas Karlman <jonas@kwiboo.se>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
arch/arm/dts/rk3399-puma-haikou-u-boot.dtsi
arch/arm/dts/rk3399-u-boot.dtsi

index 390cf24152a6c35cce07c6be5efc7e1dc73b6899..d1912a2ef6a966cd4d1e0053649c58ce6580af57 100644 (file)
 
 &uart0 {
        bootph-all;
+       clock-frequency = <24000000>;
+};
+
+&uart0_cts {
+       bootph-pre-sram;
+       bootph-pre-ram;
+};
+
+&uart0_rts {
+       bootph-pre-sram;
+       bootph-pre-ram;
+};
+
+&uart0_xfer {
+       bootph-pre-sram;
+       bootph-pre-ram;
 };
index 9815dc53e8ed96af4d513b78dd86cf322027c3de..b39fe39fa2b373ec82648b120033af423266aee0 100644 (file)
 
 &uart2 {
        bootph-all;
+       clock-frequency = <24000000>;
+};
+
+&uart2c_xfer {
+       bootph-pre-sram;
+       bootph-pre-ram;
 };
 
 &vopb {