Perform a simple rename of CONFIG_LPC32XX_NAND_SLC_WDR_CLKS to CFG_LPC32XX_NAND_SLC_WDR_CLKS
Signed-off-by: Tom Rini <trini@konsulko.com>
&lpc32xx_nand_slc_regs->icr);
/* Configure NAND flash timings */
- writel(TAC_W_RDY(CONFIG_LPC32XX_NAND_SLC_WDR_CLKS) |
+ writel(TAC_W_RDY(CFG_LPC32XX_NAND_SLC_WDR_CLKS) |
TAC_W_WIDTH(hclk / CONFIG_LPC32XX_NAND_SLC_WWIDTH) |
TAC_W_HOLD(hclk / CONFIG_LPC32XX_NAND_SLC_WHOLD) |
TAC_W_SETUP(hclk / CONFIG_LPC32XX_NAND_SLC_WSETUP) |
/*
* NAND chip timings
*/
-#define CONFIG_LPC32XX_NAND_SLC_WDR_CLKS 14
+#define CFG_LPC32XX_NAND_SLC_WDR_CLKS 14
#define CONFIG_LPC32XX_NAND_SLC_WWIDTH 66666666
#define CONFIG_LPC32XX_NAND_SLC_WHOLD 200000000
#define CONFIG_LPC32XX_NAND_SLC_WSETUP 50000000