reset: add reset controller driver for MediaTek MIPS platform

This patch adds reset controller driver for MediaTek MIPS platform and
header file for mt7628.

Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>

diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 976f3a701c58bb9e1b82f3e82edfcecf6f89cc18..cff00820e486e0025dbf07e0ede2372220b34bb8 100644 (file)
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -113,6 +113,13 @@ config RESET_MEDIATEK
        help
          Support for reset controller on MediaTek SoCs.
 
+config RESET_MTMIPS
+       bool "Reset controller driver for MediaTek MIPS platform"
+       depends on DM_RESET && ARCH_MTMIPS
+       default y
+       help
+         Support for reset controller on MediaTek MIPS platform.
+
 config RESET_SUNXI
        bool "RESET support for Allwinner SoCs"
        depends on DM_RESET && ARCH_SUNXI

diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile
index f5875fce099d01e2ad398e2bfd9c18c5ce0216c5..8102d8db2918fadfa1d2c17d1d91f6f03439767f 100644 (file)
--- a/drivers/reset/Makefile
+++ b/drivers/reset/Makefile
@@ -18,6 +18,7 @@ obj-$(CONFIG_RESET_ROCKCHIP) += reset-rockchip.o
 obj-$(CONFIG_RESET_MESON) += reset-meson.o
 obj-$(CONFIG_RESET_SOCFPGA) += reset-socfpga.o
 obj-$(CONFIG_RESET_MEDIATEK) += reset-mediatek.o
+obj-$(CONFIG_RESET_MTMIPS) += reset-mtmips.o
 obj-$(CONFIG_RESET_SUNXI) += reset-sunxi.o
 obj-$(CONFIG_RESET_HISILICON) += reset-hisilicon.o
 obj-$(CONFIG_RESET_IMX7) += reset-imx7.o

diff --git a/drivers/reset/reset-mtmips.c b/drivers/reset/reset-mtmips.c
new file mode 100644 (file)
index 0000000..5973456
--- /dev/null
+++ b/drivers/reset/reset-mtmips.c
@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (C) 2019 MediaTek Inc. All Rights Reserved.
+ *
+ * Author: Weijie Gao <weijie.gao@mediatek.com>
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <reset-uclass.h>
+#include <linux/io.h>
+
+struct mtmips_reset_priv {
+       void __iomem *base;
+};
+
+static int mtmips_reset_request(struct reset_ctl *reset_ctl)
+{
+       return 0;
+}
+
+static int mtmips_reset_free(struct reset_ctl *reset_ctl)
+{
+       return 0;
+}
+
+static int mtmips_reset_assert(struct reset_ctl *reset_ctl)
+{
+       struct mtmips_reset_priv *priv = dev_get_priv(reset_ctl->dev);
+
+       setbits_32(priv->base, BIT(reset_ctl->id));
+
+       return 0;
+}
+
+static int mtmips_reset_deassert(struct reset_ctl *reset_ctl)
+{
+       struct mtmips_reset_priv *priv = dev_get_priv(reset_ctl->dev);
+
+       clrbits_32(priv->base, BIT(reset_ctl->id));
+
+       return 0;
+}
+
+static const struct reset_ops mtmips_reset_ops = {
+       .request        = mtmips_reset_request,
+       .free           = mtmips_reset_free,
+       .rst_assert     = mtmips_reset_assert,
+       .rst_deassert   = mtmips_reset_deassert,
+};
+
+static int mtmips_reset_probe(struct udevice *dev)
+{
+       return 0;
+}
+
+static int mtmips_reset_ofdata_to_platdata(struct udevice *dev)
+{
+       struct mtmips_reset_priv *priv = dev_get_priv(dev);
+
+       priv->base = (void __iomem *)dev_remap_addr_index(dev, 0);
+       if (!priv->base)
+               return -EINVAL;
+
+       return 0;
+}
+
+static const struct udevice_id mtmips_reset_ids[] = {
+       { .compatible = "mediatek,mtmips-reset" },
+       { }
+};
+
+U_BOOT_DRIVER(mtmips_reset) = {
+       .name = "mtmips-reset",
+       .id = UCLASS_RESET,
+       .of_match = mtmips_reset_ids,
+       .ofdata_to_platdata = mtmips_reset_ofdata_to_platdata,
+       .probe = mtmips_reset_probe,
+       .priv_auto_alloc_size = sizeof(struct mtmips_reset_priv),
+       .ops = &mtmips_reset_ops,
+};

diff --git a/include/dt-bindings/reset/mt7628-reset.h b/include/dt-bindings/reset/mt7628-reset.h
new file mode 100644 (file)
index 0000000..2a674c1
--- /dev/null
+++ b/include/dt-bindings/reset/mt7628-reset.h
@@ -0,0 +1,36 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2019 MediaTek Inc.
+ *
+ * Author:  Weijie Gao <weijie.gao@mediatek.com>
+ */
+
+#ifndef _DT_BINDINGS_MT7628_RESET_H_
+#define _DT_BINDINGS_MT7628_RESET_H_
+
+#define MT7628_PWM_RST                 31
+#define MT7628_SDXC_RST                        30
+#define MT7628_CRYPTO_RST              29
+#define MT7628_AUX_STCK_RST            28
+#define MT7628_PCIE_RST                        26
+#define MT7628_EPHY_RST                        24
+#define MT7628_ETH_RST                 23
+#define MT7628_UPHY_RST                        22
+#define MT7628_UART2_RST               20
+#define MT7628_UART1_RST               19
+#define MT7628_SPI_RST                 18
+#define MT7628_I2S_RST                 17
+#define MT7628_I2C_RST                 16
+#define MT7628_GDMA_RST                        14
+#define MT7628_PIO_RST                 13
+#define MT7628_UART0_RST               12
+#define MT7628_PCM_RST                 11
+#define MT7628_MC_RST                  10
+#define MT7628_INT_RST                 9
+#define MT7628_TIMER_RST               8
+#define MT7628_HIF_RST                 5
+#define MT7628_WIFI_RST                        4
+#define MT7628_SPIS_RST                        3
+#define MT7628_SYS_RST                 0
+
+#endif /* _DT_BINDINGS_MT7628_RESET_H_ */