return 0;
}
-static int imx8_init_mu(void *ctx, struct event *event)
+static int imx8_init_mu(void)
{
struct udevice *devp;
int node, ret;
return 0;
}
-EVENT_SPY(EVT_DM_POST_INIT_F, imx8_init_mu);
+EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_F, imx8_init_mu);
#if defined(CONFIG_ARCH_MISC_INIT)
int arch_misc_init(void)
writew(enable, &wdog3->wmcr);
}
-static int imx8m_check_clock(void *ctx, struct event *event)
+static int imx8m_check_clock(void)
{
struct udevice *dev;
int ret;
return 0;
}
-EVENT_SPY(EVT_DM_POST_INIT_F, imx8m_check_clock);
+EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_F, imx8m_check_clock);
static void imx8m_setup_snvs(void)
{
return 0;
}
-
-static int imx8ulp_evt_dm_post_init(void *ctx, struct event *event)
-{
- return imx8ulp_dm_post_init();
-}
-EVENT_SPY(EVT_DM_POST_INIT_F, imx8ulp_evt_dm_post_init);
+EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_F, imx8ulp_dm_post_init);
#if defined(CONFIG_SPL_BUILD)
__weak void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image)
return 0;
}
-int imx9_probe_mu(void *ctx, struct event *event)
+int imx9_probe_mu(void)
{
struct udevice *devp;
int node, ret;
return 0;
}
-EVENT_SPY(EVT_DM_POST_INIT_F, imx9_probe_mu);
+EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_F, imx9_probe_mu);
int timer_init(void)
{
#endif
-static int am33xx_dm_post_init(void *ctx, struct event *event)
+static int am33xx_dm_post_init(void)
{
hw_data_init();
#if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
#endif
return 0;
}
-EVENT_SPY(EVT_DM_POST_INIT_F, am33xx_dm_post_init);
+EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_F, am33xx_dm_post_init);
* done in each of these cases
* This function is called with SRAM stack.
*/
-void early_system_init(void)
+int early_system_init(void)
{
#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_MULTI_DTB_FIT)
int ret;
debug_uart_init();
#endif
prcm_init();
+
+ return 0;
}
#ifdef CONFIG_SPL_BUILD
}
#endif
-static int omap2_system_init(void *ctx, struct event *event)
-{
- early_system_init();
-
- return 0;
-}
-EVENT_SPY(EVT_DM_POST_INIT_F, omap2_system_init);
+EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_F, early_system_init);
/*
* Routine: wait_for_command_complete
iounmap(regs);
}
-/* arch specific CPU init after DM */
-static int pic32_flash_prefetch(void *ctx, struct event *event)
-{
- /* flash prefetch */
- prefetch_init();
- return 0;
-}
-EVENT_SPY(EVT_DM_POST_INIT_F, pic32_flash_prefetch);
+/* arch-specific CPU init after DM: flash prefetch */
+EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_F, prefetch_init);
/* Un-gate DDR2 modules (gated by default) */
static void ddr2_pmd_ungate(void)
}
#endif
-static int nios_cpu_setup(void *ctx, struct event *event)
+static int nios_cpu_setup(void)
{
struct udevice *dev;
int ret;
return 0;
}
-EVENT_SPY(EVT_DM_POST_INIT_F, nios_cpu_setup);
+EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_F, nios_cpu_setup);
static int altera_nios2_get_desc(const struct udevice *dev, char *buf,
int size)
}
#endif
-int riscv_cpu_setup(void *ctx, struct event *event)
+int riscv_cpu_setup(void)
{
int ret;
return 0;
}
-EVENT_SPY(EVT_DM_POST_INIT_F, riscv_cpu_setup);
+EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_F, riscv_cpu_setup);
int arch_early_init_r(void)
{
} while (0)
/* Hook to set up the CPU (called from SPL too) */
-int riscv_cpu_setup(void *ctx, struct event *event);
+int riscv_cpu_setup(void);
#endif /* __ASM_RISCV_SYSTEM_H */
if (ret)
panic("spl_early_init() failed: %d\n", ret);
- riscv_cpu_setup(NULL, NULL);
+ riscv_cpu_setup();
preloader_console_init();
os_exit(0);
}
-
-static int sandbox_misc_init_f(void *ctx, struct event *event)
-{
- return sandbox_early_getopt_check();
-}
-EVENT_SPY(EVT_MISC_INIT_F, sandbox_misc_init_f);
+EVENT_SPY_SIMPLE(EVT_MISC_INIT_F, sandbox_early_getopt_check);
static int sandbox_cmdline_cb_help(struct sandbox_state *state, const char *arg)
{
* Configure the internal clock of both SIO HS-UARTs, if they are enabled
* via FSP
*/
-static int baytrail_uart_init(void *ctx, struct event *event)
+static int baytrail_uart_init(void)
{
struct udevice *dev;
void *base;
return 0;
}
-EVENT_SPY(EVT_DM_POST_INIT_F, baytrail_uart_init);
+EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_F, baytrail_uart_init);
static void set_max_freq(void)
{
#include <asm/arch/pch.h>
#include <asm/arch/rcb.h>
-static int broadwell_init_cpu(void *ctx, struct event *event)
+static int broadwell_init_cpu(void)
{
struct udevice *dev;
int ret;
return 0;
}
-EVENT_SPY(EVT_DM_POST_INIT_F, broadwell_init_cpu);
+EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_F, broadwell_init_cpu);
void set_max_freq(void)
{
return x86_cpu_init_f();
}
-static int ivybridge_cpu_init(void *ctx, struct event *ev)
+static int ivybridge_cpu_init(void)
{
struct pci_controller *hose;
struct udevice *bus, *dev;
return 0;
}
-EVENT_SPY(EVT_DM_POST_INIT_F, ivybridge_cpu_init);
+EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_F, ivybridge_cpu_init);
#define PCH_EHCI0_TEMP_BAR0 0xe8000000
#define PCH_EHCI1_TEMP_BAR0 0xe8000400
return 0;
}
-static int quark_init_pcie(void *ctx, struct event *event)
-{
- /*
- * Initialize PCIe controller
- *
- * Quark SoC holds the PCIe controller in reset following a power on.
- * U-Boot needs to release the PCIe controller from reset. The PCIe
- * controller (D23:F0/F1) will not be visible in PCI configuration
- * space and any access to its PCI configuration registers will cause
- * system hang while it is held in reset.
- */
- quark_pcie_early_init();
-
- return 0;
-}
-EVENT_SPY(EVT_DM_POST_INIT_F, quark_init_pcie);
+/*
+ * Initialize PCIe controller
+ *
+ * Quark SoC holds the PCIe controller in reset following a power on.
+ * U-Boot needs to release the PCIe controller from reset. The PCIe
+ * controller (D23:F0/F1) will not be visible in PCI configuration
+ * space and any access to its PCI configuration registers will cause
+ * system hang while it is held in reset.
+ */
+EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_F, quark_pcie_early_init);
int checkcpu(void)
{
#include <dm/uclass-internal.h>
#include <asm/fsp2/fsp_internal.h>
-int fsp_setup_pinctrl(void *ctx, struct event *event)
+int fsp_setup_pinctrl(void)
{
struct udevice *dev;
ofnode node;
return ret;
}
-EVENT_SPY(EVT_DM_POST_INIT_F, fsp_setup_pinctrl);
+EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_F, fsp_setup_pinctrl);
#if !defined(CONFIG_TPL_BUILD)
binman_sym_declare(ulong, intel_fsp_m, image_pos);
int flags;
};
-static int coral_check_ll_boot(void *ctx, struct event *event)
+static int coral_check_ll_boot(void)
{
if (!ll_boot_init()) {
printf("Running as secondary loader");
return 0;
}
-EVENT_SPY(EVT_MISC_INIT_F, coral_check_ll_boot);
+EVENT_SPY_SIMPLE(EVT_MISC_INIT_F, coral_check_ll_boot);
int arch_misc_init(void)
{
return (gd->bus_clk / 2);
}
-static int kmcent2_misc_init_f(void *ctx, struct event *event)
+static int kmcent2_misc_init_f(void)
{
/* configure QRIO pis for i2c deblocking */
i2c_deblock_gpio_cfg();
return 0;
}
-EVENT_SPY(EVT_MISC_INIT_F, kmcent2_misc_init_f);
+EVENT_SPY_SIMPLE(EVT_MISC_INIT_F, kmcent2_misc_init_f);
#define USED_SRDS_BANK 0
#define EXPECTED_SRDS_RFCK SRDS_PLLCR0_RFCK_SEL_100
return 0;
}
-static int pg_wcom_misc_init_f(void *ctx, struct event *event)
+static int pg_wcom_misc_init_f(void)
{
if (IS_ENABLED(CONFIG_PG_WCOM_UBOOT_UPDATE_SUPPORTED))
check_for_uboot_update();
return 0;
}
-EVENT_SPY(EVT_MISC_INIT_F, pg_wcom_misc_init_f);
+EVENT_SPY_SIMPLE(EVT_MISC_INIT_F, pg_wcom_misc_init_f);
int board_init(void)
{
if (ret)
panic("spl_early_init() failed: %d\n", ret);
- riscv_cpu_setup(NULL, NULL);
+ riscv_cpu_setup();
preloader_console_init();
/* Set the parent clock of cpu_root clock to pll0,
ci = tmp; \
}
-static int microblaze_cpu_probe_all(void *ctx, struct event *event)
+static int microblaze_cpu_probe_all(void)
{
int ret;
return 0;
}
-EVENT_SPY(EVT_DM_POST_INIT_F, microblaze_cpu_probe_all);
+EVENT_SPY_SIMPLE(EVT_DM_POST_INIT_F, microblaze_cpu_probe_all);
static void microblaze_set_cpuinfo_pvr(struct microblaze_cpuinfo *ci)
{
return ret;
}
-static int fwu_boottime_checks(void *ctx, struct event *event)
+static int fwu_boottime_checks(void)
{
int ret;
u32 boot_idx, active_idx;
return 0;
}
-EVENT_SPY(EVT_MAIN_LOOP, fwu_boottime_checks);
+EVENT_SPY_SIMPLE(EVT_MAIN_LOOP, fwu_boottime_checks);
-------------------- ------------------------------ ------------------------------
EVT_FT_FIXUP bootmeth_vbe_ft_fixup .*boot/vbe_request.c:.*
EVT_FT_FIXUP bootmeth_vbe_simple_ft_fixup .*boot/vbe_simple_os.c:.*
-EVT_MISC_INIT_F sandbox_misc_init_f .*arch/sandbox/cpu/start.c:.*
+EVT_MISC_INIT_F sandbox_early_getopt_check .*arch/sandbox/cpu/start.c:.*
EVT_TEST h_adder_simple .*test/common/event.c:'''
assert re.match(expect, out, re.MULTILINE) is not None