#include <asm/arch/clocks_am33xx.h>
#include <asm/arch/hardware.h>
-#if defined(CONFIG_TI816X) || defined(CONFIG_TI814X)
+#if defined(CONFIG_TI816X)
#include <asm/arch/clock_ti81xx.h>
#endif
unsigned int mmu_clkstctrl;
unsigned int mmucfg_clkstctrl;
unsigned int ocmc0clkstctrl;
-#if defined(CONFIG_TI814X)
- unsigned int vcpclkstctrl;
-#elif defined(CONFIG_TI816X)
+#if defined(CONFIG_TI816X)
unsigned int ocmc1clkstctrl;
#endif
unsigned int mpuclkstctrl;
unsigned int gpio1clkctrl;
unsigned int i2c0clkctrl;
unsigned int i2c1clkctrl;
-#if defined(CONFIG_TI814X)
- unsigned int mcasp345clkctrl;
- unsigned int atlclkctrl;
- unsigned int mlbclkctrl;
- unsigned int pataclkctrl;
- unsigned int resv1[1];
- unsigned int uart3clkctrl;
- unsigned int uart4clkctrl;
- unsigned int uart5clkctrl;
-#elif defined(CONFIG_TI816X)
+#if defined(CONFIG_TI816X)
unsigned int resv1[1];
unsigned int timer1clkctrl;
unsigned int timer2clkctrl;
unsigned int mmudataclkctrl;
unsigned int resv2[2];
unsigned int mmucfgclkctrl;
-#if defined(CONFIG_TI814X)
- unsigned int resv3[2];
-#elif defined(CONFIG_TI816X)
+#if defined(CONFIG_TI816X)
unsigned int resv3[1];
unsigned int sdioclkctrl;
#endif
unsigned int ocmc0clkctrl;
-#if defined(CONFIG_TI814X)
- unsigned int vcpclkctrl;
-#elif defined(CONFIG_TI816X)
+#if defined(CONFIG_TI816X)
unsigned int ocmc1clkctrl;
#endif
unsigned int resv4[2];
unsigned int ethernet0clkctrl;
unsigned int ethernet1clkctrl;
unsigned int mpuclkctrl;
-#if defined(CONFIG_TI814X)
- unsigned int debugssclkctrl;
-#elif defined(CONFIG_TI816X)
+#if defined(CONFIG_TI816X)
unsigned int resv6[1];
#endif
unsigned int l3clkctrl;
unsigned int tptc1clkctrl;
unsigned int tptc2clkctrl;
unsigned int tptc3clkctrl;
-#if defined(CONFIG_TI814X)
- unsigned int resv6[4];
- unsigned int dcan01clkctrl;
- unsigned int mmchs0clkctrl;
- unsigned int mmchs1clkctrl;
- unsigned int mmchs2clkctrl;
- unsigned int custefuseclkctrl;
-#elif defined(CONFIG_TI816X)
+#if defined(CONFIG_TI816X)
unsigned int sr0clkctrl;
unsigned int sr1clkctrl;
#endif
#include <asm/arch/hardware_am33xx.h>
#elif defined(CONFIG_TI816X)
#include <asm/arch/hardware_ti816x.h>
-#elif defined(CONFIG_TI814X)
-#include <asm/arch/hardware_ti814x.h>
#elif defined(CONFIG_AM43XX)
#include <asm/arch/hardware_am43xx.h>
#endif
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * hardware_ti814x.h
- *
- * TI814x hardware specific header
- *
- * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
- */
-
-#ifndef __AM33XX_HARDWARE_TI814X_H
-#define __AM33XX_HARDWARE_TI814X_H
-
-/* Module base addresses */
-
-/* UART Base Address */
-#define UART0_BASE 0x48020000
-
-/* Watchdog Timer */
-#define WDT_BASE 0x481C7000
-
-/* Control Module Base Address */
-#define CTRL_BASE 0x48140000
-#define CTRL_DEVICE_BASE 0x48140600
-
-/* PRCM Base Address */
-#define PRCM_BASE 0x48180000
-#define CM_PER 0x44E00000
-#define CM_WKUP 0x44E00400
-
-#define PRM_RSTCTRL (PRCM_BASE + 0x00A0)
-#define PRM_RSTST (PRM_RSTCTRL + 8)
-
-/* PLL Subsystem Base Address */
-#define PLL_SUBSYS_BASE 0x481C5000
-
-/* VTP Base address */
-#define VTP0_CTRL_ADDR 0x48140E0C
-#define VTP1_CTRL_ADDR 0x48140E10
-
-/* DDR Base address */
-#define DDR_PHY_CMD_ADDR 0x47C0C400
-#define DDR_PHY_DATA_ADDR 0x47C0C4C8
-#define DDR_PHY_CMD_ADDR2 0x47C0C800
-#define DDR_PHY_DATA_ADDR2 0x47C0C8C8
-#define DDR_DATA_REGS_NR 4
-
-#define DDRPHY_0_CONFIG_BASE (CTRL_BASE + 0x1400)
-#define DDRPHY_CONFIG_BASE DDRPHY_0_CONFIG_BASE
-
-/* CPSW Config space */
-#define CPSW_MDIO_BASE 0x4A100800
-
-/* RTC base address */
-#define RTC_BASE 0x480C0000
-
-/* OTG */
-#define USB0_OTG_BASE 0x47401000
-#define USB1_OTG_BASE 0x47401800
-
-#endif /* __AM33XX_HARDWARE_TI814X_H */
#define OMAP_HSMMC1_BASE 0x48060000
#define OMAP_HSMMC2_BASE 0x481D8000
-#if defined(CONFIG_TI814X)
-#undef MMC_CLOCK_REFERENCE
-#define MMC_CLOCK_REFERENCE 192 /* MHz */
-#elif defined(CONFIG_TI816X)
+#if defined(CONFIG_TI816X)
#undef MMC_CLOCK_REFERENCE
#define MMC_CLOCK_REFERENCE 48 /* MHz */
#endif
#ifdef CONFIG_AM33XX
#include <asm/arch/mux_am33xx.h>
-#elif defined(CONFIG_TI814X)
-#include <asm/arch/mux_ti814x.h>
#elif defined(CONFIG_TI816X)
#include <asm/arch/mux_ti816x.h>
#elif defined(CONFIG_AM43XX)
+++ /dev/null
-/*
- * mux_ti814x.h
- *
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef _MUX_TI814X_H_
-#define _MUX_TI814X_H_
-
-/* PAD Control Fields */
-#define PINCNTL_RSV_MSK (0x3 << 18) /* Reserved bitmask */
-#define PULLUP_EN (0x1 << 17) /* Pull UP Selection */
-#define PULLUDEN (0x0 << 16) /* Pull up enabled */
-#define PULLUDDIS (0x1 << 16) /* Pull up disabled */
-#define MODE(val) val /* used for Readability */
-
-#define MUX_CFG(value, offset) \
-{ \
- int tmp; \
- tmp = __raw_readl(CTRL_BASE + offset); \
- tmp &= PINCNTL_RSV_MSK; \
- __raw_writel(tmp | value, (CTRL_BASE + offset));\
-}
-
-/*
- * PAD CONTROL OFFSETS
- * Field names corresponds to the pad signal name
- */
-struct pad_signals {
- int pincntl1;
- int pincntl2;
- int pincntl3;
- int pincntl4;
- int pincntl5;
- int pincntl6;
- int pincntl7;
- int pincntl8;
- int pincntl9;
- int pincntl10;
- int pincntl11;
- int pincntl12;
- int pincntl13;
- int pincntl14;
- int pincntl15;
- int pincntl16;
- int pincntl17;
- int pincntl18;
- int pincntl19;
- int pincntl20;
- int pincntl21;
- int pincntl22;
- int pincntl23;
- int pincntl24;
- int pincntl25;
- int pincntl26;
- int pincntl27;
- int pincntl28;
- int pincntl29;
- int pincntl30;
- int pincntl31;
- int pincntl32;
- int pincntl33;
- int pincntl34;
- int pincntl35;
- int pincntl36;
- int pincntl37;
- int pincntl38;
- int pincntl39;
- int pincntl40;
- int pincntl41;
- int pincntl42;
- int pincntl43;
- int pincntl44;
- int pincntl45;
- int pincntl46;
- int pincntl47;
- int pincntl48;
- int pincntl49;
- int pincntl50;
- int pincntl51;
- int pincntl52;
- int pincntl53;
- int pincntl54;
- int pincntl55;
- int pincntl56;
- int pincntl57;
- int pincntl58;
- int pincntl59;
- int pincntl60;
- int pincntl61;
- int pincntl62;
- int pincntl63;
- int pincntl64;
- int pincntl65;
- int pincntl66;
- int pincntl67;
- int pincntl68;
- int pincntl69;
- int pincntl70;
- int pincntl71;
- int pincntl72;
- int pincntl73;
- int pincntl74;
- int pincntl75;
- int pincntl76;
- int pincntl77;
- int pincntl78;
- int pincntl79;
- int pincntl80;
- int pincntl81;
- int pincntl82;
- int pincntl83;
- int pincntl84;
- int pincntl85;
- int pincntl86;
- int pincntl87;
- int pincntl88;
- int pincntl89;
- int pincntl90;
- int pincntl91;
- int pincntl92;
- int pincntl93;
- int pincntl94;
- int pincntl95;
- int pincntl96;
- int pincntl97;
- int pincntl98;
- int pincntl99;
- int pincntl100;
- int pincntl101;
- int pincntl102;
- int pincntl103;
- int pincntl104;
- int pincntl105;
- int pincntl106;
- int pincntl107;
- int pincntl108;
- int pincntl109;
- int pincntl110;
- int pincntl111;
- int pincntl112;
- int pincntl113;
- int pincntl114;
- int pincntl115;
- int pincntl116;
- int pincntl117;
- int pincntl118;
- int pincntl119;
- int pincntl120;
- int pincntl121;
- int pincntl122;
- int pincntl123;
- int pincntl124;
- int pincntl125;
- int pincntl126;
- int pincntl127;
- int pincntl128;
- int pincntl129;
- int pincntl130;
- int pincntl131;
- int pincntl132;
- int pincntl133;
- int pincntl134;
- int pincntl135;
- int pincntl136;
- int pincntl137;
- int pincntl138;
- int pincntl139;
- int pincntl140;
- int pincntl141;
- int pincntl142;
- int pincntl143;
- int pincntl144;
- int pincntl145;
- int pincntl146;
- int pincntl147;
- int pincntl148;
- int pincntl149;
- int pincntl150;
- int pincntl151;
- int pincntl152;
- int pincntl153;
- int pincntl154;
- int pincntl155;
- int pincntl156;
- int pincntl157;
- int pincntl158;
- int pincntl159;
- int pincntl160;
- int pincntl161;
- int pincntl162;
- int pincntl163;
- int pincntl164;
- int pincntl165;
- int pincntl166;
- int pincntl167;
- int pincntl168;
- int pincntl169;
- int pincntl170;
- int pincntl171;
- int pincntl172;
- int pincntl173;
- int pincntl174;
- int pincntl175;
- int pincntl176;
- int pincntl177;
- int pincntl178;
- int pincntl179;
- int pincntl180;
- int pincntl181;
- int pincntl182;
- int pincntl183;
- int pincntl184;
- int pincntl185;
- int pincntl186;
- int pincntl187;
- int pincntl188;
- int pincntl189;
- int pincntl190;
- int pincntl191;
- int pincntl192;
- int pincntl193;
- int pincntl194;
- int pincntl195;
- int pincntl196;
- int pincntl197;
- int pincntl198;
- int pincntl199;
- int pincntl200;
- int pincntl201;
- int pincntl202;
- int pincntl203;
- int pincntl204;
- int pincntl205;
- int pincntl206;
- int pincntl207;
- int pincntl208;
- int pincntl209;
- int pincntl210;
- int pincntl211;
- int pincntl212;
- int pincntl213;
- int pincntl214;
- int pincntl215;
- int pincntl216;
- int pincntl217;
- int pincntl218;
- int pincntl219;
- int pincntl220;
- int pincntl221;
- int pincntl222;
- int pincntl223;
- int pincntl224;
- int pincntl225;
- int pincntl226;
- int pincntl227;
- int pincntl228;
- int pincntl229;
- int pincntl230;
- int pincntl231;
- int pincntl232;
- int pincntl233;
- int pincntl234;
- int pincntl235;
- int pincntl236;
- int pincntl237;
- int pincntl238;
- int pincntl239;
- int pincntl240;
- int pincntl241;
- int pincntl242;
- int pincntl243;
- int pincntl244;
- int pincntl245;
- int pincntl246;
- int pincntl247;
- int pincntl248;
- int pincntl249;
- int pincntl250;
- int pincntl251;
- int pincntl252;
- int pincntl253;
- int pincntl254;
- int pincntl255;
- int pincntl256;
- int pincntl257;
- int pincntl258;
- int pincntl259;
- int pincntl260;
- int pincntl261;
- int pincntl262;
- int pincntl263;
- int pincntl264;
- int pincntl265;
- int pincntl266;
- int pincntl267;
- int pincntl268;
- int pincntl269;
- int pincntl270;
-};
-
-#endif /* endif _MUX_TI814X_H_ */
#define NON_SECURE_SRAM_START 0x402F0400
#define NON_SECURE_SRAM_END 0x40310000
#define NON_SECURE_SRAM_IMG_END 0x4030B800
-#elif defined(CONFIG_TI816X) || defined(CONFIG_TI814X)
+#elif defined(CONFIG_TI816X)
#define NON_SECURE_SRAM_START 0x40300000
#define NON_SECURE_SRAM_END 0x40320000
#define NON_SECURE_SRAM_IMG_END 0x4031B800
#define BOOT_DEVICE_NONE 0x00
#define BOOT_DEVICE_MMC2_2 0xFF
-#if defined(CONFIG_TI814X)
-#define BOOT_DEVICE_XIP 0x01
-#define BOOT_DEVICE_XIPWAIT 0x02
-#define BOOT_DEVICE_NAND 0x05
-#define BOOT_DEVICE_NAND_I2C 0x06
-#define BOOT_DEVICE_MMC2 0x08 /* ROM only supports 2nd instance. */
-#define BOOT_DEVICE_MMC1 0x09
-#define BOOT_DEVICE_SPI 0x15
-#define BOOT_DEVICE_UART 0x41
-#define BOOT_DEVICE_USBETH 0x44
-#define BOOT_DEVICE_CPGMAC 0x46
-
-#define MMC_BOOT_DEVICES_START BOOT_DEVICE_MMC2
-#define MMC_BOOT_DEVICES_END BOOT_DEVICE_MMC1
-#elif defined(CONFIG_TI816X)
+#if defined(CONFIG_TI816X)
#define BOOT_DEVICE_XIP 0x01
#define BOOT_DEVICE_XIPWAIT 0x02
#define BOOT_DEVICE_NAND 0x03
imply SPL_SERIAL
imply SYS_I2C_OMAP24XX
-config TI814X
- bool "TI814X SoC"
- select SPECIFY_CONSOLE_INDEX
- help
- Support for AM335x SOC from Texas Instruments.
- The AM335x high performance SOC features a Cortex-A8
- ARM core and more.
-
config TI816X
bool "TI816X SoC"
select SPECIFY_CONSOLE_INDEX
endif
-if TI814X
-
-config TARGET_TI814X_EVM
- bool "Support ti814x_evm"
- help
- This option specifies support for the TI8148
- EVM development platform.
-
-endif
-
if AM33XX
config AM33XX_CHILISOM
# Copyright (C) 2011, Texas Instruments, Incorporated - http://www.ti.com/
obj-$(CONFIG_AM33XX) += clock_am33xx.o
-obj-$(CONFIG_TI814X) += clock_ti814x.o
obj-$(CONFIG_AM43XX) += clock_am43xx.o
ifneq ($(CONFIG_AM43XX)$(CONFIG_AM33XX),)
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * clock_ti814x.c
- *
- * Clocks for TI814X based boards
- *
- * Copyright (C) 2013, Texas Instruments, Incorporated
- */
-
-#include <common.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/hardware.h>
-#include <asm/io.h>
-#include <linux/delay.h>
-
-/* PRCM */
-#define PRCM_MOD_EN 0x2
-
-/* CLK_SRC */
-#define OSC_SRC0 0
-#define OSC_SRC1 1
-
-#define L3_OSC_SRC OSC_SRC0
-
-#define OSC_0_FREQ 20
-
-#define DCO_HS2_MIN 500
-#define DCO_HS2_MAX 1000
-#define DCO_HS1_MIN 1000
-#define DCO_HS1_MAX 2000
-
-#define SELFREQDCO_HS2 0x00000801
-#define SELFREQDCO_HS1 0x00001001
-
-#define MPU_N 0x1
-#define MPU_M 0x3C
-#define MPU_M2 1
-#define MPU_CLKCTRL 0x1
-
-#define L3_N 19
-#define L3_M 880
-#define L3_M2 4
-#define L3_CLKCTRL 0x801
-
-#define DDR_N 19
-#define DDR_M 666
-#define DDR_M2 2
-#define DDR_CLKCTRL 0x801
-
-/* ADPLLJ register values */
-#define ADPLLJ_CLKCTRL_HS2 0x00000801 /* HS2 mode, TINT2 = 1 */
-#define ADPLLJ_CLKCTRL_HS1 0x00001001 /* HS1 mode, TINT2 = 1 */
-#define ADPLLJ_CLKCTRL_CLKDCOLDOEN (1 << 29)
-#define ADPLLJ_CLKCTRL_IDLE (1 << 23)
-#define ADPLLJ_CLKCTRL_CLKOUTEN (1 << 20)
-#define ADPLLJ_CLKCTRL_CLKOUTLDOEN (1 << 19)
-#define ADPLLJ_CLKCTRL_CLKDCOLDOPWDNZ (1 << 17)
-#define ADPLLJ_CLKCTRL_LPMODE (1 << 12)
-#define ADPLLJ_CLKCTRL_DRIFTGUARDIAN (1 << 11)
-#define ADPLLJ_CLKCTRL_REGM4XEN (1 << 10)
-#define ADPLLJ_CLKCTRL_TINITZ (1 << 0)
-#define ADPLLJ_CLKCTRL_CLKDCO (ADPLLJ_CLKCTRL_CLKDCOLDOEN | \
- ADPLLJ_CLKCTRL_CLKOUTEN | \
- ADPLLJ_CLKCTRL_CLKOUTLDOEN | \
- ADPLLJ_CLKCTRL_CLKDCOLDOPWDNZ)
-
-#define ADPLLJ_STATUS_PHASELOCK (1 << 10)
-#define ADPLLJ_STATUS_FREQLOCK (1 << 9)
-#define ADPLLJ_STATUS_PHSFRQLOCK (ADPLLJ_STATUS_PHASELOCK | \
- ADPLLJ_STATUS_FREQLOCK)
-#define ADPLLJ_STATUS_BYPASSACK (1 << 8)
-#define ADPLLJ_STATUS_BYPASS (1 << 0)
-#define ADPLLJ_STATUS_BYPASSANDACK (ADPLLJ_STATUS_BYPASSACK | \
- ADPLLJ_STATUS_BYPASS)
-
-#define ADPLLJ_TENABLE_ENB (1 << 0)
-#define ADPLLJ_TENABLEDIV_ENB (1 << 0)
-
-#define ADPLLJ_M2NDIV_M2SHIFT 16
-
-#define MPU_PLL_BASE (PLL_SUBSYS_BASE + 0x048)
-#define L3_PLL_BASE (PLL_SUBSYS_BASE + 0x110)
-#define DDR_PLL_BASE (PLL_SUBSYS_BASE + 0x290)
-
-struct ad_pll {
- unsigned int pwrctrl;
- unsigned int clkctrl;
- unsigned int tenable;
- unsigned int tenablediv;
- unsigned int m2ndiv;
- unsigned int mn2div;
- unsigned int fracdiv;
- unsigned int bwctrl;
- unsigned int fracctrl;
- unsigned int status;
- unsigned int m3div;
- unsigned int rampctrl;
-};
-
-#define OSC_SRC_CTRL (PLL_SUBSYS_BASE + 0x2C0)
-
-#define ENET_CLKCTRL_CMPL 0x30000
-
-#define SATA_PLL_BASE (CTRL_BASE + 0x0720)
-
-struct sata_pll {
- unsigned int pllcfg0;
- unsigned int pllcfg1;
- unsigned int pllcfg2;
- unsigned int pllcfg3;
- unsigned int pllcfg4;
- unsigned int pllstatus;
- unsigned int rxstatus;
- unsigned int txstatus;
- unsigned int testcfg;
-};
-
-#define SEL_IN_FREQ (0x1 << 31)
-#define DIGCLRZ (0x1 << 30)
-#define ENDIGLDO (0x1 << 4)
-#define APLL_CP_CURR (0x1 << 3)
-#define ENBGSC_REF (0x1 << 2)
-#define ENPLLLDO (0x1 << 1)
-#define ENPLL (0x1 << 0)
-
-#define SATA_PLLCFG0_1 (SEL_IN_FREQ | ENBGSC_REF)
-#define SATA_PLLCFG0_2 (SEL_IN_FREQ | ENDIGLDO | ENBGSC_REF)
-#define SATA_PLLCFG0_3 (SEL_IN_FREQ | ENDIGLDO | ENBGSC_REF | ENPLLLDO)
-#define SATA_PLLCFG0_4 (SEL_IN_FREQ | DIGCLRZ | ENDIGLDO | ENBGSC_REF | \
- ENPLLLDO | ENPLL)
-
-#define PLL_LOCK (0x1 << 0)
-
-#define ENSATAMODE (0x1 << 31)
-#define PLLREFSEL (0x1 << 30)
-#define MDIVINT (0x4b << 18)
-#define EN_CLKAUX (0x1 << 5)
-#define EN_CLK125M (0x1 << 4)
-#define EN_CLK100M (0x1 << 3)
-#define EN_CLK50M (0x1 << 2)
-
-#define SATA_PLLCFG1 (ENSATAMODE | \
- PLLREFSEL | \
- MDIVINT | \
- EN_CLKAUX | \
- EN_CLK125M | \
- EN_CLK100M | \
- EN_CLK50M)
-
-#define DIGLDO_EN_CAPLESSMODE (0x1 << 22)
-#define PLLDO_EN_LDO_STABLE (0x1 << 11)
-#define PLLDO_EN_BUF_CUR (0x1 << 7)
-#define PLLDO_EN_LP (0x1 << 6)
-#define PLLDO_CTRL_TRIM_1_4V (0x10 << 1)
-
-#define SATA_PLLCFG3 (DIGLDO_EN_CAPLESSMODE | \
- PLLDO_EN_LDO_STABLE | \
- PLLDO_EN_BUF_CUR | \
- PLLDO_EN_LP | \
- PLLDO_CTRL_TRIM_1_4V)
-
-const struct cm_alwon *cmalwon = (struct cm_alwon *)CM_ALWON_BASE;
-const struct cm_def *cmdef = (struct cm_def *)CM_DEFAULT_BASE;
-const struct sata_pll *spll = (struct sata_pll *)SATA_PLL_BASE;
-
-/*
- * Enable the peripheral clock for required peripherals
- */
-static void enable_per_clocks(void)
-{
- /* HSMMC1 */
- writel(PRCM_MOD_EN, &cmalwon->mmchs1clkctrl);
- while (readl(&cmalwon->mmchs1clkctrl) != PRCM_MOD_EN)
- ;
-
- /* Ethernet */
- writel(PRCM_MOD_EN, &cmalwon->ethclkstctrl);
- writel(PRCM_MOD_EN, &cmalwon->ethernet0clkctrl);
- while ((readl(&cmalwon->ethernet0clkctrl) & ENET_CLKCTRL_CMPL) != 0)
- ;
- writel(PRCM_MOD_EN, &cmalwon->ethernet1clkctrl);
- while ((readl(&cmalwon->ethernet1clkctrl) & ENET_CLKCTRL_CMPL) != 0)
- ;
-
- /* RTC clocks */
- writel(PRCM_MOD_EN, &cmalwon->rtcclkstctrl);
- writel(PRCM_MOD_EN, &cmalwon->rtcclkctrl);
- while (readl(&cmalwon->rtcclkctrl) != PRCM_MOD_EN)
- ;
-}
-
-/*
- * select the HS1 or HS2 for DCO Freq
- * return : CLKCTRL
- */
-static u32 pll_dco_freq_sel(u32 clkout_dco)
-{
- if (clkout_dco >= DCO_HS2_MIN && clkout_dco < DCO_HS2_MAX)
- return SELFREQDCO_HS2;
- else if (clkout_dco >= DCO_HS1_MIN && clkout_dco < DCO_HS1_MAX)
- return SELFREQDCO_HS1;
- else
- return -1;
-}
-
-/*
- * select the sigma delta config
- * return: sigma delta val
- */
-static u32 pll_sigma_delta_val(u32 clkout_dco)
-{
- u32 sig_val = 0;
-
- sig_val = (clkout_dco + 225) / 250;
- sig_val = sig_val << 24;
-
- return sig_val;
-}
-
-/*
- * configure individual ADPLLJ
- */
-static void pll_config(u32 base, u32 n, u32 m, u32 m2,
- u32 clkctrl_val, int adpllj)
-{
- const struct ad_pll *adpll = (struct ad_pll *)base;
- u32 m2nval, mn2val, read_clkctrl = 0, clkout_dco = 0;
- u32 sig_val = 0, hs_mod = 0;
-
- m2nval = (m2 << ADPLLJ_M2NDIV_M2SHIFT) | n;
- mn2val = m;
-
- /* calculate clkout_dco */
- clkout_dco = ((OSC_0_FREQ / (n+1)) * m);
-
- /* sigma delta & Hs mode selection skip for ADPLLS*/
- if (adpllj) {
- sig_val = pll_sigma_delta_val(clkout_dco);
- hs_mod = pll_dco_freq_sel(clkout_dco);
- }
-
- /* by-pass pll */
- read_clkctrl = readl(&adpll->clkctrl);
- writel((read_clkctrl | ADPLLJ_CLKCTRL_IDLE), &adpll->clkctrl);
- while ((readl(&adpll->status) & ADPLLJ_STATUS_BYPASSANDACK)
- != ADPLLJ_STATUS_BYPASSANDACK)
- ;
-
- /* clear TINITZ */
- read_clkctrl = readl(&adpll->clkctrl);
- writel((read_clkctrl & ~ADPLLJ_CLKCTRL_TINITZ), &adpll->clkctrl);
-
- /*
- * ref_clk = 20/(n + 1);
- * clkout_dco = ref_clk * m;
- * clk_out = clkout_dco/m2;
- */
- read_clkctrl = readl(&adpll->clkctrl) &
- ~(ADPLLJ_CLKCTRL_LPMODE |
- ADPLLJ_CLKCTRL_DRIFTGUARDIAN |
- ADPLLJ_CLKCTRL_REGM4XEN);
- writel(m2nval, &adpll->m2ndiv);
- writel(mn2val, &adpll->mn2div);
-
- /* Skip for modena(ADPLLS) */
- if (adpllj) {
- writel(sig_val, &adpll->fracdiv);
- writel((read_clkctrl | hs_mod), &adpll->clkctrl);
- }
-
- /* Load M2, N2 dividers of ADPLL */
- writel(ADPLLJ_TENABLEDIV_ENB, &adpll->tenablediv);
- writel(~ADPLLJ_TENABLEDIV_ENB, &adpll->tenablediv);
-
- /* Load M, N dividers of ADPLL */
- writel(ADPLLJ_TENABLE_ENB, &adpll->tenable);
- writel(~ADPLLJ_TENABLE_ENB, &adpll->tenable);
-
- /* Configure CLKDCOLDOEN,CLKOUTLDOEN,CLKOUT Enable BITS */
- read_clkctrl = readl(&adpll->clkctrl) & ~ADPLLJ_CLKCTRL_CLKDCO;
- if (adpllj)
- writel((read_clkctrl | ADPLLJ_CLKCTRL_CLKDCO),
- &adpll->clkctrl);
-
- /* Enable TINTZ and disable IDLE(PLL in Active & Locked Mode */
- read_clkctrl = readl(&adpll->clkctrl) & ~ADPLLJ_CLKCTRL_IDLE;
- writel((read_clkctrl | ADPLLJ_CLKCTRL_TINITZ), &adpll->clkctrl);
-
- /* Wait for phase and freq lock */
- while ((readl(&adpll->status) & ADPLLJ_STATUS_PHSFRQLOCK) !=
- ADPLLJ_STATUS_PHSFRQLOCK)
- ;
-}
-
-static void unlock_pll_control_mmr(void)
-{
- /* TRM 2.10.1.4 and 3.2.7-3.2.11 */
- writel(0x1EDA4C3D, 0x481C5040);
- writel(0x2FF1AC2B, 0x48140060);
- writel(0xF757FDC0, 0x48140064);
- writel(0xE2BC3A6D, 0x48140068);
- writel(0x1EBF131D, 0x4814006c);
- writel(0x6F361E05, 0x48140070);
-}
-
-static void mpu_pll_config(void)
-{
- pll_config(MPU_PLL_BASE, MPU_N, MPU_M, MPU_M2, MPU_CLKCTRL, 0);
-}
-
-static void l3_pll_config(void)
-{
- u32 l3_osc_src, rd_osc_src = 0;
-
- l3_osc_src = L3_OSC_SRC;
- rd_osc_src = readl(OSC_SRC_CTRL);
-
- if (OSC_SRC0 == l3_osc_src)
- writel((rd_osc_src & 0xfffffffe)|0x0, OSC_SRC_CTRL);
- else
- writel((rd_osc_src & 0xfffffffe)|0x1, OSC_SRC_CTRL);
-
- pll_config(L3_PLL_BASE, L3_N, L3_M, L3_M2, L3_CLKCTRL, 1);
-}
-
-void ddr_pll_config(unsigned int ddrpll_m)
-{
- pll_config(DDR_PLL_BASE, DDR_N, DDR_M, DDR_M2, DDR_CLKCTRL, 1);
-}
-
-void sata_pll_config(void)
-{
- /*
- * This sequence for configuring the SATA PLL
- * resident in the control module is documented
- * in TI8148 TRM section 21.3.1
- */
- writel(SATA_PLLCFG1, &spll->pllcfg1);
- udelay(50);
-
- writel(SATA_PLLCFG3, &spll->pllcfg3);
- udelay(50);
-
- writel(SATA_PLLCFG0_1, &spll->pllcfg0);
- udelay(50);
-
- writel(SATA_PLLCFG0_2, &spll->pllcfg0);
- udelay(50);
-
- writel(SATA_PLLCFG0_3, &spll->pllcfg0);
- udelay(50);
-
- writel(SATA_PLLCFG0_4, &spll->pllcfg0);
- udelay(50);
-
- while (((readl(&spll->pllstatus) & PLL_LOCK) == 0))
- ;
-}
-
-void enable_dmm_clocks(void)
-{
- writel(PRCM_MOD_EN, &cmdef->fwclkctrl);
- writel(PRCM_MOD_EN, &cmdef->l3fastclkstctrl);
- writel(PRCM_MOD_EN, &cmdef->emif0clkctrl);
- while ((readl(&cmdef->emif0clkctrl)) != PRCM_MOD_EN)
- ;
- writel(PRCM_MOD_EN, &cmdef->emif1clkctrl);
- while ((readl(&cmdef->emif1clkctrl)) != PRCM_MOD_EN)
- ;
- while ((readl(&cmdef->l3fastclkstctrl) & 0x300) != 0x300)
- ;
- writel(PRCM_MOD_EN, &cmdef->dmmclkctrl);
- while ((readl(&cmdef->dmmclkctrl)) != PRCM_MOD_EN)
- ;
- writel(PRCM_MOD_EN, &cmalwon->l3slowclkstctrl);
- while ((readl(&cmalwon->l3slowclkstctrl) & 0x2100) != 0x2100)
- ;
-}
-
-void setup_clocks_for_console(void)
-{
- unlock_pll_control_mmr();
- /* UART0 */
- writel(PRCM_MOD_EN, &cmalwon->uart0clkctrl);
- while (readl(&cmalwon->uart0clkctrl) != PRCM_MOD_EN)
- ;
-}
-
-void setup_early_clocks(void)
-{
- setup_clocks_for_console();
-}
-
-/*
- * Configure the PLL/PRCM for necessary peripherals
- */
-void prcm_init(void)
-{
- /* Enable the control module */
- writel(PRCM_MOD_EN, &cmalwon->controlclkctrl);
-
- /* Configure PLLs */
- mpu_pll_config();
- l3_pll_config();
- sata_pll_config();
-
- /* Enable the required peripherals */
- enable_per_clocks();
-}
(struct cm_device_inst *)CM_DEVICE_INST;
#endif
-#ifdef CONFIG_TI814X
-void config_dmm(const struct dmm_lisa_map_regs *regs)
-{
- struct dmm_lisa_map_regs *hw_lisa_map_regs =
- (struct dmm_lisa_map_regs *)DMM_BASE;
-
- enable_dmm_clocks();
-
- writel(0, &hw_lisa_map_regs->dmm_lisa_map_3);
- writel(0, &hw_lisa_map_regs->dmm_lisa_map_2);
- writel(0, &hw_lisa_map_regs->dmm_lisa_map_1);
- writel(0, &hw_lisa_map_regs->dmm_lisa_map_0);
-
- writel(regs->dmm_lisa_map_3, &hw_lisa_map_regs->dmm_lisa_map_3);
- writel(regs->dmm_lisa_map_2, &hw_lisa_map_regs->dmm_lisa_map_2);
- writel(regs->dmm_lisa_map_1, &hw_lisa_map_regs->dmm_lisa_map_1);
- writel(regs->dmm_lisa_map_0, &hw_lisa_map_regs->dmm_lisa_map_0);
-}
-#endif
-
static void config_vtp(int nr)
{
writel(readl(&vtpreg[nr]->vtp0ctrlreg) | VTP_CTRL_ENABLE,
gd->arch.omap_boot_mode = boot_mode;
-#if !defined(CONFIG_TI814X) && !defined(CONFIG_TI816X) && \
+#if !defined(CONFIG_TI816X) && \
!defined(CONFIG_AM33XX) && !defined(CONFIG_AM43XX)
/* CH flags */
depends on ARCH_OMAP2PLUS || ARCH_SOCFPGA
default 2 if TI816X
default 3 if OMAP34XX || AM33XX || AM43XX
- default 4 if ARCH_SOCFPGA || OMAP44XX || TI814X
+ default 4 if ARCH_SOCFPGA || OMAP44XX
default 5 if OMAP54XX
help
Define the maximum number of available I2C buses.
u32 tx_pri_map;
#ifdef CONFIG_AM33XX
u32 gap_thresh;
-#elif defined(CONFIG_TI814X)
- u32 ts_ctl;
- u32 ts_seq_ltype;
- u32 ts_vlan;
#endif
u32 sa_lo;
u32 sa_hi;
+++ /dev/null
-/*
- * ti814x_evm.h
- *
- * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation version 2.
- *
- * This program is distributed "as is" WITHOUT ANY WARRANTY of any
- * kind, whether express or implied; without even the implied warranty
- * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef __CONFIG_TI814X_EVM_H
-#define __CONFIG_TI814X_EVM_H
-
-#include <asm/arch/omap.h>
-
-/* commands to include */
-
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "loadaddr=0x80200000\0" \
- "fdtaddr=0x80F80000\0" \
- "rdaddr=0x81000000\0" \
- "bootfile=/boot/uImage\0" \
- "fdtfile=\0" \
- "console=ttyO0,115200n8\0" \
- "optargs=\0" \
- "mmcdev=0\0" \
- "mmcroot=/dev/mmcblk0p2 ro\0" \
- "mmcrootfstype=ext4 rootwait\0" \
- "ramroot=/dev/ram0 rw ramdisk_size=65536 initrd=${rdaddr},64M\0" \
- "ramrootfstype=ext2\0" \
- "mmcargs=setenv bootargs console=${console} " \
- "${optargs} " \
- "root=${mmcroot} " \
- "rootfstype=${mmcrootfstype}\0" \
- "bootenv=uEnv.txt\0" \
- "loadbootenv=fatload mmc ${mmcdev} ${loadaddr} ${bootenv}\0" \
- "importbootenv=echo Importing environment from mmc ...; " \
- "env import -t $loadaddr $filesize\0" \
- "ramargs=setenv bootargs console=${console} " \
- "${optargs} " \
- "root=${ramroot} " \
- "rootfstype=${ramrootfstype}\0" \
- "loadramdisk=fatload mmc ${mmcdev} ${rdaddr} ramdisk.gz\0" \
- "loaduimagefat=fatload mmc ${mmcdev} ${loadaddr} ${bootfile}\0" \
- "loaduimage=ext2load mmc ${mmcdev}:2 ${loadaddr} ${bootfile}\0" \
- "mmcboot=echo Booting from mmc ...; " \
- "run mmcargs; " \
- "bootm ${loadaddr}\0" \
- "ramboot=echo Booting from ramdisk ...; " \
- "run ramargs; " \
- "bootm ${loadaddr}\0" \
- "fdtfile=ti814x-evm.dtb\0" \
-
-/* Clock Defines */
-#define V_OSCK 24000000 /* Clock output from T2 */
-#define V_SCLK (V_OSCK >> 1)
-
-
-/* Console I/O Buffer Size */
-
-/**
- * Physical Memory Map
- */
-#define PHYS_DRAM_1_SIZE 0x20000000 /* 512MB */
-#define CONFIG_MAX_RAM_BANK_SIZE (1024 << 20) /* 1024MB */
-
-#define CFG_SYS_SDRAM_BASE 0x80000000
-
-/**
- * Platform/Board specific defs
- */
-#define CFG_SYS_TIMERBASE 0x4802E000
-
-/* NS16550 Configuration */
-#define CFG_SYS_NS16550_CLK (48000000)
-#define CFG_SYS_NS16550_COM1 0x48020000 /* Base EVM has UART0 */
-
-/* CPU */
-
-/* Defines for SPL */
-
-/*
- * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
- * 64 bytes before this address should be set aside for u-boot.img's
- * header. That is 0x800FFFC0--0x80800000 should not be used for any
- * other needs.
- */
-
-/*
- * Since SPL did pll and ddr initialization for us,
- * we don't need to do it twice.
- */
-
-/* Ethernet */
-#define CONFIG_PHY_ET1011C_TX_CLK_FIX
-
-#endif /* ! __CONFIG_TI814X_EVM_H */
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