mx6dlsabresd: Use its own DCD table

Currently mx6dlsabresd shares the same DCD settings with the nitrogen board.

Provide a DCD configuration file specific to mx6dlsabresd with the settings
recommended by the Freescale hardware team.

Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>

diff --git a/board/freescale/mx6sabresd/mx6dlsabresd.cfg b/board/freescale/mx6sabresd/mx6dlsabresd.cfg
new file mode 100644 (file)
index 0000000..f35f22e
--- /dev/null
+++ b/board/freescale/mx6sabresd/mx6dlsabresd.cfg
@@ -0,0 +1,131 @@
+/*
+ * Copyright (C) 2014 Freescale Semiconductor, Inc.
+ *
+ * SPDX-License-Identifier:    GPL-2.0+
+ *
+ * Refer docs/README.imxmage for more details about how-to configure
+ * and create imximage boot image
+ *
+ * The syntax is taken as close as possible with the kwbimage
+ */
+
+/* image version */
+
+IMAGE_VERSION 2
+
+/*
+ * Boot Device : one of
+ * spi, sd (the board has no nand neither onenand)
+ */
+
+BOOT_FROM      sd
+
+/*
+ * Device Configuration Data (DCD)
+ *
+ * Each entry must have the format:
+ * Addr-type           Address        Value
+ *
+ * where:
+ *     Addr-type register length (1,2 or 4 bytes)
+ *     Address   absolute address of the register
+ *     value     value to be stored in the register
+ */
+DATA 4 0x020e0774 0x000C0000
+DATA 4 0x020e0754 0x00000000
+DATA 4 0x020e04ac 0x00000030
+DATA 4 0x020e04b0 0x00000030
+DATA 4 0x020e0464 0x00000030
+DATA 4 0x020e0490 0x00000030
+DATA 4 0x020e074c 0x00000030
+DATA 4 0x020e0494 0x00000030
+DATA 4 0x020e04a0 0x00000000
+DATA 4 0x020e04b4 0x00000030
+DATA 4 0x020e04b8 0x00000030
+DATA 4 0x020e076c 0x00000030
+DATA 4 0x020e0750 0x00020000
+DATA 4 0x020e04bc 0x00000030
+DATA 4 0x020e04c0 0x00000030
+DATA 4 0x020e04c4 0x00000030
+DATA 4 0x020e04c8 0x00000030
+DATA 4 0x020e04cc 0x00000030
+DATA 4 0x020e04d0 0x00000030
+DATA 4 0x020e04d4 0x00000030
+DATA 4 0x020e04d8 0x00000030
+DATA 4 0x020e0760 0x00020000
+DATA 4 0x020e0764 0x00000030
+DATA 4 0x020e0770 0x00000030
+DATA 4 0x020e0778 0x00000030
+DATA 4 0x020e077c 0x00000030
+DATA 4 0x020e0780 0x00000030
+DATA 4 0x020e0784 0x00000030
+DATA 4 0x020e078c 0x00000030
+DATA 4 0x020e0748 0x00000030
+DATA 4 0x020e0470 0x00000030
+DATA 4 0x020e0474 0x00000030
+DATA 4 0x020e0478 0x00000030
+DATA 4 0x020e047c 0x00000030
+DATA 4 0x020e0480 0x00000030
+DATA 4 0x020e0484 0x00000030
+DATA 4 0x020e0488 0x00000030
+DATA 4 0x020e048c 0x00000030
+DATA 4 0x021b0800 0xa1390003
+DATA 4 0x021b080c 0x001F001F
+DATA 4 0x021b0810 0x001F001F
+DATA 4 0x021b480c 0x001F001F
+DATA 4 0x021b4810 0x001F001F
+DATA 4 0x021b083c 0x4220021F
+DATA 4 0x021b0840 0x0207017E
+DATA 4 0x021b483c 0x4201020C
+DATA 4 0x021b4840 0x01660172
+DATA 4 0x021b0848 0x4A4D4E4D
+DATA 4 0x021b4848 0x4A4F5049
+DATA 4 0x021b0850 0x3F3C3D31
+DATA 4 0x021b4850 0x3238372B
+DATA 4 0x021b081c 0x33333333
+DATA 4 0x021b0820 0x33333333
+DATA 4 0x021b0824 0x33333333
+DATA 4 0x021b0828 0x33333333
+DATA 4 0x021b481c 0x33333333
+DATA 4 0x021b4820 0x33333333
+DATA 4 0x021b4824 0x33333333
+DATA 4 0x021b4828 0x33333333
+DATA 4 0x021b08b8 0x00000800
+DATA 4 0x021b48b8 0x00000800
+DATA 4 0x021b0004 0x0002002D
+DATA 4 0x021b0008 0x00333030
+DATA 4 0x021b000c 0x3F435313
+DATA 4 0x021b0010 0xB66E8B63
+DATA 4 0x021b0014 0x01FF00DB
+DATA 4 0x021b0018 0x00001740
+DATA 4 0x021b001c 0x00008000
+DATA 4 0x021b002c 0x000026d2
+DATA 4 0x021b0030 0x00431023
+DATA 4 0x021b0040 0x00000027
+DATA 4 0x021b0000 0x831A0000
+DATA 4 0x021b001c 0x04008032
+DATA 4 0x021b001c 0x00008033
+DATA 4 0x021b001c 0x00048031
+DATA 4 0x021b001c 0x05208030
+DATA 4 0x021b001c 0x04008040
+DATA 4 0x021b0020 0x00005800
+DATA 4 0x021b0818 0x00011117
+DATA 4 0x021b4818 0x00011117
+DATA 4 0x021b0004 0x0002556D
+DATA 4 0x021b0404 0x00011006
+DATA 4 0x021b001c 0x00000000
+
+/* set the default clock gate to save power */
+DATA 4 0x020c4068 0x00C03F3F
+DATA 4 0x020c406c 0x0030FC03
+DATA 4 0x020c4070 0x0FFFC000
+DATA 4 0x020c4074 0x3FF00000
+DATA 4 0x020c4078 0x00FFF300
+DATA 4 0x020c407c 0x0F0000C3
+DATA 4 0x020c4080 0x000003FF
+
+/* enable AXI cache for VDOA/VPU/IPU */
+DATA 4 0x020e0010 0xF00000CF
+/* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
+DATA 4 0x020e0018 0x007F007F
+DATA 4 0x020e001c 0x007F007F

diff --git a/configs/mx6dlsabresd_defconfig b/configs/mx6dlsabresd_defconfig
index 9ce960e0d5611b714f98949beb2eb8b3e75c1ed5..7f6cdff384127f9d11fdb66cf063ad9fd3678725 100644 (file)
--- a/configs/mx6dlsabresd_defconfig
+++ b/configs/mx6dlsabresd_defconfig
@@ -1,3 +1,3 @@
-CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/boundary/nitrogen6x/nitrogen6dl.cfg,MX6DL"
+CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/freescale/mx6sabresd/mx6dlsabresd.cfg,MX6DL"
 CONFIG_ARM=y
 CONFIG_TARGET_MX6SABRESD=y