Drop all duplicate newlines. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
#define GMAC0_INTR_RECV_LAZY_ADDR (GMAC0_REG_BASE + 0x100)
#define GMAC0_PHY_CTRL_ADDR (GMAC0_REG_BASE + 0x188)
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#define GMAC_DMA_PTR_OFFSET 0x04
#define GMAC_DMA_ADDR_LOW_OFFSET 0x08
#define GMAC_DMA_ADDR_HIGH_OFFSET 0x0c
* Copyright 2019-2021 Broadcom.
*/
-
#include <asm/io.h>
#include <dm.h>
#include <linux/delay.h>
#define MII_REGMSK (0x1F << 6)
#define MII_ADDRMSK (0x1F << 11)
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struct eth_dma_regs {
u32 busmode; /* 0x00 */
u32 txpolldemand; /* 0x04 */
***************************************************************************/
/*******************************************************************************
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Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved.
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Contact Information:
Linux NICS <linux.nics@intel.com>
Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC;
E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1);
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switch (hw->mac_type) {
case e1000_igb: /* IGB is cool */
return;
return ret_val;
}
-
} else {
if (hw->mac_type == e1000_ich8lan) {
E1000_WRITE_REG(hw, TARC1, tarc);
}
-
e1000_config_collision_dist(hw);
/* Setup Transmit Descriptor Settings for eop descriptor */
hw->txd_cmd = E1000_TXD_CMD_EOP | E1000_TXD_CMD_IFCS;
else
hw->txd_cmd |= E1000_TXD_CMD_RS;
-
if (hw->mac_type == e1000_igb) {
E1000_WRITE_REG(hw, TCTL_EXT, 0x42 << 10);
/* SPDX-License-Identifier: GPL-2.0+ */
/*******************************************************************************
-
Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved.
Copyright 2011 Freescale Semiconductor, Inc.
off */
#define IFE_PSCL_PROBE_LEDS_ON 0x0007 /* Force LEDs 0 and 2 on */
-
#define NUM_DEV_IDS 16
#define NODE_ADDRESS_SIZE 6
e1000_ffe_config_blocked
} e1000_ffe_config;
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/* Structure containing variables used by the shared code (e1000_hw.c) */
struct e1000_hw {
const char *name;
/* In-Band Control Register (Page 194, Register 18) */
#define GG82563_ICR_DIS_PADDING 0x0010 /* Disable Padding Use */
-
/* Bits...
* 15-5: page
* 4-0: register offset
qb_attr_code_encode(&code_eq_rsp_stash, cl, !!stash);
}
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void qbman_eq_desc_set_qd(struct qbman_eq_desc *d, uint32_t qdid,
uint32_t qd_bin, uint32_t qd_prio)
{
#define QBMAN_DQRR_RESPONSE_BPSCN 0x29
#define QBMAN_DQRR_RESPONSE_CSCN_WQ 0x2a
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/* NULL return if there are no unconsumed DQRR entries. Returns a DQRR entry
* only once, so repeated calls can return a sequence of DQRR entries, without
* requiring they be consumed immediately or in any particular order. */
#define QBMAN_VER_4_0_DQRR_SIZE 4
#define QBMAN_VER_4_1_DQRR_SIZE 8
-
/* --------------------- */
/* portal data structure */
/* --------------------- */
return d32_uint32_t(code->lsoffset, code->width, cacheline[code->word]);
}
-
/* encode a field to a cacheline */
static inline void qb_attr_code_encode(const struct qb_attr_code *code,
uint32_t *cacheline, uint32_t val)
/* set the ethernet address */
ftmac100_set_mac(priv, enetaddr);
-
/* disable all interrupts */
writel (0, &ftmac100->imr);
void (*set_to_rgmii)(struct gmac_rockchip_plat *pdata);
};
-
static int gmac_rockchip_of_to_plat(struct udevice *dev)
{
struct gmac_rockchip_plat *pdata = dev_get_plat(dev);
#define TXSR_TXFID_SHIFT (0)
#define TXSR_TXFID_GET(_v) (((_v) >> 0) & 0x3f)
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#define KS_RXCR1 0x74
#define RXCR1_FRXQ (1 << 15)
#define RXCR1_RXUDPFCC (1 << 14)
#include <fsl-mc/fsl_qbman_portal.h>
#include <fsl-mc/fsl_mc_private.h>
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enum ldpaa_eth_type {
LDPAA_ETH_1G_E,
LDPAA_ETH_10G_E,
}
}
-
/*TODO what it do */
static int wriop_dpmac_to_index(int dpmac_id)
{
return dpmac_info[i].enabled;
}
-
int wriop_set_mdio(int dpmac_id, struct mii_dev *bus)
{
int i = wriop_dpmac_to_index(dpmac_id);
#define GEM_SGMIIEN_OFFSET 27
#define GEM_SGMIIEN_SIZE 1
-
/* Constants for data bus width. */
#define GEM_DBW32 0 /* 32 bit AMBA AHB data bus width */
#define GEM_DBW64 1 /* 64 bit AMBA AHB data bus width */
#define GEM_ADDR64_OFFSET 30 /* Address bus width - 64b or 32b */
#define GEM_ADDR64_SIZE 1
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/* Bitfields in NSR */
#define MACB_NSR_LINK_OFFSET 0 /* pcs_link_state */
#define MACB_NSR_LINK_SIZE 1
#define GEM_TX_PKT_BUFF_OFFSET 21
#define GEM_TX_PKT_BUFF_SIZE 1
-
/* Bitfields in DCFG5. */
#define GEM_TSU_OFFSET 8
#define GEM_TSU_SIZE 1
return 0;
}
-
static void fec_stop(struct udevice *dev)
{
struct ether_fcc_info_s *efis = dev_get_priv(dev);
GCB_MISC_STAT_PHY_READY, true, 500, false))
return -EACCES;
-
/* Initialize miim buses */
memset(&miim, 0x0, sizeof(miim) * LUTON_MIIM_BUS_COUNT);
phys_addr_t miim_base,
unsigned long miim_size);
-
#endif /* _MSCC_MIIM_H_ */
return &pp->rxqs[rxq];
}
-
/* Drop packets received by the RXQ and free buffers */
static void mvneta_rxq_drop_pkts(struct mvneta_port *pp,
struct mvneta_rx_queue *rxq)
mvneta_rxq_deinit(pp, &pp->rxqs[queue]);
}
-
/* Init all Rx queues */
static int mvneta_setup_rxqs(struct mvneta_port *pp)
{
port->rxqs[queue] = rxq;
}
-
/* Create Rx descriptor rings */
for (queue = 0; queue < rxq_number; queue++) {
struct mvpp2_rx_queue *rxq = port->rxqs[queue];
if (gem->phy_mode == PHY_INTERFACE_MODE_2500BASEX)
sgmii_2500 = 1;
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/* PCS configuration done with corresponding GEMAC */
bus.priv = gem_info[priv->gemac_port].gemac_base;
#define MIIM_DM9161_10BTCSR 0x12
#define MIIM_DM9161_10BTCSR_INIT 0x7800
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/* Davicom DM9161E */
static int dm9161_config(struct phy_device *phydev)
{
#define MIIM_LXT971_SR2_100HDX 0x4000 /* 100 Mbit half duplex selected */
#define MIIM_LXT971_SR2_100FDX 0x4200 /* 100 Mbit full duplex selected */
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/* LXT971 */
static int lxt971_parse_status(struct phy_device *phydev)
{
return phy_read(phydev, MDIO_DEVAD_NONE, MII_KSZ9021_EXTENDED_DATAR);
}
-
static int ksz9021_phy_extread(struct phy_device *phydev, int addr, int devaddr,
int regnum)
{
return rdreg;
}
-
/*****************************************************************************
*
* Write a MII PHY register.
return ret;
}
-
int do_mvsw_reg(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[])
{
int ret;
.shutdown = &genphy_shutdown,
};
-
/* DP83865 Link and Auto-Neg Status Register */
#define MIIM_DP83865_LANR 0x11
#define MIIM_DP83865_SPD_MASK 0x0018
#define MIIM_DP83865_SPD_100 0x0008
#define MIIM_DP83865_DPX_FULL 0x0002
-
/* NatSemi DP83865 */
static int dp838xx_config(struct phy_device *phydev)
{
return dp83865_parse_status(phydev);
}
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U_BOOT_PHY_DRIVER(dp83865) = {
.name = "NatSemi DP83865",
.uid = 0x20005c70,
RTL_W32(TxConfig, (TX_DMA_BURST << TxDMAShift) |
(InterFrameGap << TxInterFrameGapShift));
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tpc->cur_rx = 0;
RTL_W32(TxDescStartAddrLow, dm_pci_mem_to_phys(dev,
#endif
}
-
tpc->RxDescArray = rtl_alloc_descs(NUM_RX_DESC);
if (!tpc->RxDescArray)
return -ENOMEM;
EESR_PRE = 0x00000002, EESR_CERF = 0x00000001,
};
-
#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)
# define TX_CHECK (EESR_TC1 | EESR_FTC)
# define EESR_ERR_CHECK (EESR_TWB | EESR_TABT | EESR_RABT | EESR_RDE \
struct udevice *phy_reg;
};
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struct sun8i_eth_pdata {
struct eth_pdata eth_pdata;
u32 reset_delays[3];
int rx_delay_ps;
};
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static int sun8i_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
{
struct udevice *dev = bus->priv;
writel(mac_hi, &adap_emac->MACSRCADDRHI);
writel(mac_lo, &adap_emac->MACSRCADDRLO);
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return 0;
}
return count;
}
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/* Read a PHY register via MDIO inteface. Returns 1 on success, 0 otherwise */
int davinci_eth_phy_read(u_int8_t phy_addr, u_int8_t reg_num, u_int16_t *data)
{
}
/* End of generic PHY functions */
-
#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII)
static int davinci_mii_phy_read(struct mii_dev *bus, int addr, int devad,
int reg)
*/
#define EMAC_MAX_RX_BUFFERS 10
-
/***********************************************
******** Internally used macros ***************
***********************************************/
/* Number of statistics registers */
#define EMAC_NUM_STATS 36
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/* EMAC Descriptor */
typedef volatile struct _emac_desc
{
#define EMAC_RXMBPENABLE_RXCAFEN_ENABLE (0x200000)
#define EMAC_RXMBPENABLE_RXBROADEN (0x2000)
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#define MDIO_CONTROL_IDLE (0x80000000)
#define MDIO_CONTROL_ENABLE (0x40000000)
#define MDIO_CONTROL_FAULT_ENABLE (0x40000)
#endif
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struct ks2_eth_priv {
struct udevice *dev;
struct phy_device *phydev;
__raw_writel(mr_adv_ability, SGMII_MRADV_REG(port));
__raw_writel(control, SGMII_CTL_REG(port));
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mask = SGMII_REG_STATUS_LINK;
if (control & SGMII_REG_CONTROL_AUTONEG)
return phy_config(priv->phydev);
}
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static int zynq_gem_init(struct udevice *dev)
{
u32 i, nwconfig, nwcfg;