#include <asm/asi.h>
#include <asm/leon.h>
#include <ambapp.h>
+#include <grlib/irqmp.h>
+#include <grlib/gptimer.h>
#include <config.h>
/* reset CPU (jump to 0, without reset) */
void start(void);
-/* find & initialize the memory controller */
-int init_memory_ctrl(void);
-
ambapp_dev_irqmp *irqmp = NULL;
-ambapp_dev_mctrl memctrl;
ambapp_dev_gptimer *gptimer = NULL;
unsigned int gptimer_irq = 0;
int leon3_snooping_avail = 0;
gptimer->e[0].val = 0;
gptimer->e[0].rld = (TIMER_BASE_CLK / CONFIG_SYS_HZ) - 1;
gptimer->e[0].ctrl =
- (LEON3_GPTIMER_EN |
- LEON3_GPTIMER_RL | LEON3_GPTIMER_LD | LEON3_GPTIMER_IRQEN);
+ (GPTIMER_CTRL_EN | GPTIMER_CTRL_RS |
+ GPTIMER_CTRL_LD | GPTIMER_CTRL_IE);
return gptimer_irq;
}
#include <asm/leon.h>
#include <ambapp.h>
+#include <grlib/irqmp.h>
+#include <grlib/gptimer.h>
/* 15 normal irqs and a non maskable interrupt */
#define NR_IRQS 15
/* Handle Timer 0 IRQ */
void timer_interrupt_cpu(void *arg)
{
- gptimer->e[0].ctrl = (LEON3_GPTIMER_EN |
- LEON3_GPTIMER_RL |
- LEON3_GPTIMER_LD | LEON3_GPTIMER_IRQEN);
+ gptimer->e[0].ctrl = (GPTIMER_CTRL_EN | GPTIMER_CTRL_RS |
+ GPTIMER_CTRL_LD | GPTIMER_CTRL_IE);
/* nothing to do here */
return;
}
#include <asm/irq.h>
#include <asm/leon.h>
#include <ambapp.h>
+#include <grlib/apbuart.h>
+#include <grlib/irqmp.h>
+#include <grlib/gptimer.h>
#include <config.h>
/*
/* Wait for last character to go. */
while (!(SPARC_BYPASS_READ(&uart->status)
- & LEON_REG_UART_STATUS_THE)) ;
+ & APBUART_STATUS_THE));
/* Send data */
SPARC_BYPASS_WRITE(&uart->data, c);
/* Wait for data to be sent */
while (!(SPARC_BYPASS_READ(&uart->status)
- & LEON_REG_UART_STATUS_TSE)) ;
+ & APBUART_STATUS_TSE));
return 0;
}
#include <common.h>
#include <asm/io.h>
#include <ambapp.h>
+#include <grlib/apbuart.h>
#include <serial.h>
#include <watchdog.h>
writel(tmp, &uart->scaler);
/* Let bit 11 be unchanged (debug bit for GRMON) */
- tmp = readl(&uart->ctrl) & LEON_REG_UART_CTRL_DBG;
+ tmp = readl(&uart->ctrl) & APBUART_CTRL_DBG;
/* Receiver & transmitter enable */
- tmp |= LEON_REG_UART_CTRL_RE | LEON_REG_UART_CTRL_TE;
+ tmp |= APBUART_CTRL_RE | APBUART_CTRL_TE;
writel(tmp, &uart->ctrl);
gd->arch.uart = uart;
return;
/* Wait for last character to go. */
- while (!(readl(&uart->status) & LEON_REG_UART_STATUS_THE))
+ while (!(readl(&uart->status) & APBUART_STATUS_THE))
WATCHDOG_RESET();
/* Send data */
#ifdef LEON_DEBUG
/* Wait for data to be sent */
- while (!(readl(&uart->status) & LEON_REG_UART_STATUS_TSE))
+ while (!(readl(&uart->status) & APBUART_STATUS_TSE))
WATCHDOG_RESET();
#endif
}
return 0;
/* Wait for a character to arrive. */
- while (!(readl(&uart->status) & LEON_REG_UART_STATUS_DR))
+ while (!(readl(&uart->status) & APBUART_STATUS_DR))
WATCHDOG_RESET();
/* Read character data */
if (!uart)
return 0;
- return readl(&uart->status) & LEON_REG_UART_STATUS_DR;
+ return readl(&uart->status) & APBUART_STATUS_DR;
}
/* set baud rate for uart */
{GAISLER_ASCS, "ASCS", "ASCS Master"},
{GAISLER_IPMVBCTRL, "IPMVBCTRL", "IPM-bus/MVBC memory controller"},
{GAISLER_SPIMCTRL, "SPIMCTRL", "SPI Memory Controller"},
+ {GAISLER_L4STAT, "L4STAT", "Leon4 Statistics Module"},
{GAISLER_LEON4, "LEON4", "Leon4 SPARC V8 Processor"},
{GAISLER_LEON4DSU, "LEON4DSU", "Leon4 Debug Support Unit"},
{GAISLER_PWM, "PWM", "PWM generator"},
{GAISLER_L2CACHE, "L2CACHE", "L2-Cache Controller"},
- {GAISLER_SDCTRL64, "SDCTRL64", ""},
+ {GAISLER_SDCTRL64, "SDCTRL64", "64-bit PC133 SDRAM Controller"},
+ {GAISLER_GR1553B, "GR1553B", "MIL-STD-1553B Interface"},
+ {GAISLER_1553TST, "1553TST", "MIL-STD-1553B Test Device"},
+ {GAISLER_GRIOMMU, "GRIOMMU", "I/O Memory Management Unit"},
{GAISLER_FTAHBRAM, "FTAHBRAM", "Generic FT AHB SRAM module"},
{GAISLER_FTSRCTRL, "FTSRCTRL", "Simple FT SRAM Controller"},
{GAISLER_AHBSTAT, "AHBSTAT", "AHB Status Register"},
{GAISLER_FTMCTRL, "FTMCTRL", "Memory controller with EDAC"},
{GAISLER_FTSDCTRL, "FTSDCTRL", "FT PC133 SDRAM Controller"},
{GAISLER_FTSRCTRL8, "FTSRCTRL8", "FT 8-bit SRAM/16-bit IO Ctrl"},
+ {GAISLER_MEMSCRUB, "MEMSCRUB", "AHB Memory Scrubber"},
+ {GAISLER_FTSDCTRL64, "FTSDCTRL64", "64-bit FT SDRAM Controller"},
{GAISLER_APBPS2, "APBPS2", "PS2 interface"},
{GAISLER_VGACTRL, "VGACTRL", "VGA controller"},
{GAISLER_LOGAN, "LOGAN", "On chip Logic Analyzer"},
{GAISLER_TEST_1X2, "TEST_1X2", "HAPS TEST_1x2 interface"},
{GAISLER_WILD2AHB, "WILD2AHB", "WildCard CardBus interface"},
{GAISLER_BIO1, "BIO1", "Basic I/O board BIO1"},
+ {GAISLER_AESDMA, "AESDMA", "AES 256 DMA"},
{GAISLER_SATCAN, "SATCAN", "SatCAN controller"},
{GAISLER_CANMUX, "CANMUX", "CAN Bus multiplexer"},
{GAISLER_GRTMRX, "GRTMRX", "CCSDS Telemetry Receiver"},
{GAISLER_GRTMDESC, "GRTMDESC", "CCSDS Telemetry Descriptor"},
{GAISLER_GRTMVC, "GRTMVC", "CCSDS Telemetry VC Generator"},
{GAISLER_GEFFE, "GEFFE", "Geffe Generator"},
- {GAISLER_GPREG, "GPREG", ""},
+ {GAISLER_GPREG, "GPREG", "General Purpose Register"},
{GAISLER_GRTMPAHB, "GRTMPAHB", "CCSDS Telemetry VC AHB Input"},
+ {GAISLER_SPWCUC, "SPWCUC", "CCSDS CUC / SpaceWire I/F"},
+ {GAISLER_SPW2_DMA, "SPW2_DMA", "GRSPW Router DMA interface"},
+ {GAISLER_SPWROUTER, "SPWROUTER", "GRSPW Router"},
{0, NULL, NULL}
};
};
+/** Vendor S3 devices */
+static ambapp_device_name S3_devices[] = {
+ {0, NULL, NULL}
+};
+
+
/** Vendor ACTEL devices */
static ambapp_device_name ACTEL_devices[] = {
{ACTEL_COREMP7, "COREMP7", "CoreMP7 Processor"},
{VENDOR_ORBITA, "ORBITA", "Orbita", ORBITA_devices},
{VENDOR_SYNOPSYS, "SYNOPSYS", "Synopsys Inc.", SYNOPSYS_devices},
{VENDOR_NASA, "NASA", "NASA", NASA_devices},
+ {VENDOR_S3, "S3", "S3 Group", S3_devices},
{VENDOR_CAL, "CAL", "", CAL_devices},
{VENDOR_EMBEDDIT, "EMBEDDIT", "Embedd.it", EMBEDDIT_devices},
{VENDOR_CETON, "CETON", "Ceton Corporation", CETON_devices},
#include <ambapp.h>
#include <asm/leon.h>
-#include "greth.h"
+#include <grlib/greth.h>
/* Default to 3s timeout on autonegotiation */
#ifndef GRETH_PHY_TIMEOUT_MS
#define amba_apb_mask(iobar) ((~(amba_membar_mask(iobar)<<8) & 0x000fffff) + 1)
-/*************************** AMBA Plug&Play device register MAPS *****************/
-
-/*
- * The following defines the bits in the LEON UART Status Registers.
- */
-
-#define LEON_REG_UART_STATUS_DR 0x00000001 /* Data Ready */
-#define LEON_REG_UART_STATUS_TSE 0x00000002 /* TX Send Register Empty */
-#define LEON_REG_UART_STATUS_THE 0x00000004 /* TX Hold Register Empty */
-#define LEON_REG_UART_STATUS_BR 0x00000008 /* Break Error */
-#define LEON_REG_UART_STATUS_OE 0x00000010 /* RX Overrun Error */
-#define LEON_REG_UART_STATUS_PE 0x00000020 /* RX Parity Error */
-#define LEON_REG_UART_STATUS_FE 0x00000040 /* RX Framing Error */
-#define LEON_REG_UART_STATUS_ERR 0x00000078 /* Error Mask */
-
-/*
- * The following defines the bits in the LEON UART Ctrl Registers.
- */
-
-#define LEON_REG_UART_CTRL_RE 0x00000001 /* Receiver enable */
-#define LEON_REG_UART_CTRL_TE 0x00000002 /* Transmitter enable */
-#define LEON_REG_UART_CTRL_RI 0x00000004 /* Receiver interrupt enable */
-#define LEON_REG_UART_CTRL_TI 0x00000008 /* Transmitter interrupt enable */
-#define LEON_REG_UART_CTRL_PS 0x00000010 /* Parity select */
-#define LEON_REG_UART_CTRL_PE 0x00000020 /* Parity enable */
-#define LEON_REG_UART_CTRL_FL 0x00000040 /* Flow control enable */
-#define LEON_REG_UART_CTRL_LB 0x00000080 /* Loop Back enable */
-#define LEON_REG_UART_CTRL_DBG (1<<11) /* Debug Bit used by GRMON */
-
-#define LEON3_GPTIMER_EN 1
-#define LEON3_GPTIMER_RL 2
-#define LEON3_GPTIMER_LD 4
-#define LEON3_GPTIMER_IRQEN 8
-
-/*
- * The following defines the bits in the LEON PS/2 Status Registers.
- */
-
-#define LEON_REG_PS2_STATUS_DR 0x00000001 /* Data Ready */
-#define LEON_REG_PS2_STATUS_PE 0x00000002 /* Parity error */
-#define LEON_REG_PS2_STATUS_FE 0x00000004 /* Framing error */
-#define LEON_REG_PS2_STATUS_KI 0x00000008 /* Keyboard inhibit */
-
-/*
- * The following defines the bits in the LEON PS/2 Ctrl Registers.
- */
-
-#define LEON_REG_PS2_CTRL_RE 0x00000001 /* Receiver enable */
-#define LEON_REG_PS2_CTRL_TE 0x00000002 /* Transmitter enable */
-#define LEON_REG_PS2_CTRL_RI 0x00000004 /* Keyboard receive interrupt */
-#define LEON_REG_PS2_CTRL_TI 0x00000008 /* Keyboard transmit interrupt */
-
-#ifndef __ASSEMBLER__
-
-typedef struct {
- volatile unsigned int ilevel;
- volatile unsigned int ipend;
- volatile unsigned int iforce;
- volatile unsigned int iclear;
- volatile unsigned int mstatus;
- volatile unsigned int notused[11];
- volatile unsigned int cpu_mask[16];
- volatile unsigned int cpu_force[16];
-} ambapp_dev_irqmp;
-
-typedef struct {
- volatile unsigned int data;
- volatile unsigned int status;
- volatile unsigned int ctrl;
- volatile unsigned int scaler;
-} ambapp_dev_apbuart;
-
-typedef struct {
- volatile unsigned int val;
- volatile unsigned int rld;
- volatile unsigned int ctrl;
- volatile unsigned int unused;
-} ambapp_dev_gptimer_element;
-
-#define LEON3_GPTIMER_CTRL_EN 0x1 /* Timer enable */
-#define LEON3_GPTIMER_CTRL_RS 0x2 /* Timer reStart */
-#define LEON3_GPTIMER_CTRL_LD 0x4 /* Timer reLoad */
-#define LEON3_GPTIMER_CTRL_IE 0x8 /* interrupt enable */
-#define LEON3_GPTIMER_CTRL_IP 0x10 /* interrupt flag/pending */
-#define LEON3_GPTIMER_CTRL_CH 0x20 /* Chain with previous timer */
-
-typedef struct {
- volatile unsigned int scalar;
- volatile unsigned int scalar_reload;
- volatile unsigned int config;
- volatile unsigned int unused;
- volatile ambapp_dev_gptimer_element e[8];
-} ambapp_dev_gptimer;
-
-typedef struct {
- volatile unsigned int iodata;
- volatile unsigned int ioout;
- volatile unsigned int iodir;
- volatile unsigned int irqmask;
- volatile unsigned int irqpol;
- volatile unsigned int irqedge;
-} ambapp_dev_ioport;
-
-typedef struct {
- volatile unsigned int write;
- volatile unsigned int dummy;
- volatile unsigned int txcolor;
- volatile unsigned int bgcolor;
-} ambapp_dev_textvga;
-
-typedef struct {
- volatile unsigned int data;
- volatile unsigned int status;
- volatile unsigned int ctrl;
-} ambapp_dev_apbps2;
-
-typedef struct {
- unsigned int mcfg1, mcfg2, mcfg3;
-} ambapp_dev_mctrl;
-
-typedef struct {
- unsigned int sdcfg;
-} ambapp_dev_sdctrl;
-
-typedef struct {
- unsigned int cfg1;
- unsigned int cfg2;
- unsigned int cfg3;
-} ambapp_dev_ddr2spa;
-
-typedef struct {
- unsigned int ctrl;
- unsigned int cfg;
-} ambapp_dev_ddrspa;
-
-#endif
-
#endif
#define VENDOR_ORBITA 0x17
#define VENDOR_SYNOPSYS 0x21
#define VENDOR_NASA 0x22
+#define VENDOR_S3 0x31
#define VENDOR_CAL 0xca
#define VENDOR_EMBEDDIT 0xea
#define VENDOR_CETON 0xcb
#define GAISLER_ASCS 0x043
#define GAISLER_IPMVBCTRL 0x044
#define GAISLER_SPIMCTRL 0x045
+#define GAISLER_L4STAT 0x047
#define GAISLER_LEON4 0x048
#define GAISLER_LEON4DSU 0x049
#define GAISLER_PWM 0x04a
#define GAISLER_L2CACHE 0x04b
#define GAISLER_SDCTRL64 0x04c
+#define GAISLER_GR1553B 0x04d
+#define GAISLER_1553TST 0x04e
+#define GAISLER_GRIOMMU 0x04f
#define GAISLER_FTAHBRAM 0x050
#define GAISLER_FTSRCTRL 0x051
#define GAISLER_AHBSTAT 0x052
#define GAISLER_FTMCTRL 0x054
#define GAISLER_FTSDCTRL 0x055
#define GAISLER_FTSRCTRL8 0x056
+#define GAISLER_MEMSCRUB 0x057
+#define GAISLER_FTSDCTRL64 0x058
#define GAISLER_APBPS2 0x060
#define GAISLER_VGACTRL 0x061
#define GAISLER_LOGAN 0x062
#define GAISLER_TEST_1X2 0x078
#define GAISLER_WILD2AHB 0x079
#define GAISLER_BIO1 0x07a
+#define GAISLER_AESDMA 0x07b
#define GAISLER_SATCAN 0x080
#define GAISLER_CANMUX 0x081
#define GAISLER_GRTMRX 0x082
#define GAISLER_GEFFE 0x086
#define GAISLER_GPREG 0x087
#define GAISLER_GRTMPAHB 0x088
+#define GAISLER_SPWCUC 0x089
+#define GAISLER_SPW2_DMA 0x08a
+#define GAISLER_SPWROUTER 0x08b
/* European Space Agency device ID defines */
#define ESA_LEON2 0x002
--- /dev/null
+/* GRLIB APBUART definitions
+ *
+ * (C) Copyright 2010, 2015
+ * Daniel Hellstrom, Cobham Gaisler, daniel@gaisler.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __GRLIB_APBUART_H__
+#define __GRLIB_APBUART_H__
+
+/* APBUART Register map */
+typedef struct {
+ volatile unsigned int data;
+ volatile unsigned int status;
+ volatile unsigned int ctrl;
+ volatile unsigned int scaler;
+} ambapp_dev_apbuart;
+
+/*
+ * The following defines the bits in the LEON UART Status Registers.
+ */
+
+#define APBUART_STATUS_DR 0x00000001 /* Data Ready */
+#define APBUART_STATUS_TSE 0x00000002 /* TX Send Register Empty */
+#define APBUART_STATUS_THE 0x00000004 /* TX Hold Register Empty */
+#define APBUART_STATUS_BR 0x00000008 /* Break Error */
+#define APBUART_STATUS_OE 0x00000010 /* RX Overrun Error */
+#define APBUART_STATUS_PE 0x00000020 /* RX Parity Error */
+#define APBUART_STATUS_FE 0x00000040 /* RX Framing Error */
+#define APBUART_STATUS_ERR 0x00000078 /* Error Mask */
+
+/*
+ * The following defines the bits in the LEON UART Ctrl Registers.
+ */
+
+#define APBUART_CTRL_RE 0x00000001 /* Receiver enable */
+#define APBUART_CTRL_TE 0x00000002 /* Transmitter enable */
+#define APBUART_CTRL_RI 0x00000004 /* Receiver interrupt enable */
+#define APBUART_CTRL_TI 0x00000008 /* Transmitter interrupt enable */
+#define APBUART_CTRL_PS 0x00000010 /* Parity select */
+#define APBUART_CTRL_PE 0x00000020 /* Parity enable */
+#define APBUART_CTRL_FL 0x00000040 /* Flow control enable */
+#define APBUART_CTRL_LB 0x00000080 /* Loop Back enable */
+#define APBUART_CTRL_DBG (1<<11) /* Debug Bit used by GRMON */
+
+#endif
--- /dev/null
+/* GRLIB GPTIMER (General Purpose Timer) definitions
+ *
+ * (C) Copyright 2010, 2015
+ * Daniel Hellstrom, Cobham Gaisler, daniel@gaisler.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __GRLIB_GPTIMER_H__
+#define __GRLIB_GPTIMER_H__
+
+typedef struct {
+ volatile unsigned int val;
+ volatile unsigned int rld;
+ volatile unsigned int ctrl;
+ volatile unsigned int unused;
+} ambapp_dev_gptimer_element;
+
+#define GPTIMER_CTRL_EN 0x1 /* Timer enable */
+#define GPTIMER_CTRL_RS 0x2 /* Timer reStart */
+#define GPTIMER_CTRL_LD 0x4 /* Timer reLoad */
+#define GPTIMER_CTRL_IE 0x8 /* interrupt enable */
+#define GPTIMER_CTRL_IP 0x10 /* interrupt flag/pending */
+#define GPTIMER_CTRL_CH 0x20 /* Chain with previous timer */
+
+typedef struct {
+ volatile unsigned int scalar;
+ volatile unsigned int scalar_reload;
+ volatile unsigned int config;
+ volatile unsigned int unused;
+ volatile ambapp_dev_gptimer_element e[8];
+} ambapp_dev_gptimer;
+
+#endif
--- /dev/null
+/* Gaisler.com GRETH 10/100/1000 Ethernet MAC definitions
+ *
+ * (C) Copyright 2010, 2015
+ * Daniel Hellstrom, Cobham Gaisler, daniel@gaisler.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __GRLIB_GRETH_H__
+#define __GRLIB_GRETH_H__
+
+#define GRETH_FD 0x10
+#define GRETH_RESET 0x40
+#define GRETH_MII_BUSY 0x8
+#define GRETH_MII_NVALID 0x10
+
+/* MII registers */
+#define GRETH_MII_EXTADV_1000FD 0x00000200
+#define GRETH_MII_EXTADV_1000HD 0x00000100
+#define GRETH_MII_EXTPRT_1000FD 0x00000800
+#define GRETH_MII_EXTPRT_1000HD 0x00000400
+
+#define GRETH_MII_100T4 0x00000200
+#define GRETH_MII_100TXFD 0x00000100
+#define GRETH_MII_100TXHD 0x00000080
+#define GRETH_MII_10FD 0x00000040
+#define GRETH_MII_10HD 0x00000020
+
+#define GRETH_BD_EN 0x800
+#define GRETH_BD_WR 0x1000
+#define GRETH_BD_IE 0x2000
+#define GRETH_BD_LEN 0x7FF
+
+#define GRETH_TXEN 0x1
+#define GRETH_INT_TX 0x8
+#define GRETH_TXI 0x4
+#define GRETH_TXBD_STATUS 0x0001C000
+#define GRETH_TXBD_MORE 0x20000
+#define GRETH_TXBD_IPCS 0x40000
+#define GRETH_TXBD_TCPCS 0x80000
+#define GRETH_TXBD_UDPCS 0x100000
+#define GRETH_TXBD_ERR_LC 0x10000
+#define GRETH_TXBD_ERR_UE 0x4000
+#define GRETH_TXBD_ERR_AL 0x8000
+#define GRETH_TXBD_NUM 128
+#define GRETH_TXBD_NUM_MASK (GRETH_TXBD_NUM-1)
+#define GRETH_TX_BUF_SIZE 2048
+
+#define GRETH_INT_RX 0x4
+#define GRETH_RXEN 0x2
+#define GRETH_RXI 0x8
+#define GRETH_RXBD_STATUS 0xFFFFC000
+#define GRETH_RXBD_ERR_AE 0x4000
+#define GRETH_RXBD_ERR_FT 0x8000
+#define GRETH_RXBD_ERR_CRC 0x10000
+#define GRETH_RXBD_ERR_OE 0x20000
+#define GRETH_RXBD_ERR_LE 0x40000
+#define GRETH_RXBD_IP_DEC 0x80000
+#define GRETH_RXBD_IP_CSERR 0x100000
+#define GRETH_RXBD_UDP_DEC 0x200000
+#define GRETH_RXBD_UDP_CSERR 0x400000
+#define GRETH_RXBD_TCP_DEC 0x800000
+#define GRETH_RXBD_TCP_CSERR 0x1000000
+
+#define GRETH_RXBD_NUM 128
+#define GRETH_RXBD_NUM_MASK (GRETH_RXBD_NUM-1)
+#define GRETH_RX_BUF_SIZE 2048
+
+/* Ethernet configuration registers */
+typedef struct _greth_regs {
+ volatile unsigned int control;
+ volatile unsigned int status;
+ volatile unsigned int esa_msb;
+ volatile unsigned int esa_lsb;
+ volatile unsigned int mdio;
+ volatile unsigned int tx_desc_p;
+ volatile unsigned int rx_desc_p;
+ volatile unsigned int edcl_ip;
+} greth_regs;
+
+/* Ethernet buffer descriptor */
+typedef struct _greth_bd {
+ volatile unsigned int stat;
+ unsigned int addr; /* Buffer address not changed by HW */
+} greth_bd;
+
+#endif
--- /dev/null
+/* GRLIB IRQMP (IRQ Multi-processor controller) definitions
+ *
+ * (C) Copyright 2010, 2015
+ * Daniel Hellstrom, Cobham Gaisler, daniel@gaisler.com
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#ifndef __GRLIB_IRQMP_H__
+#define __GRLIB_IRQMP_H__
+
+typedef struct {
+ volatile unsigned int ilevel;
+ volatile unsigned int ipend;
+ volatile unsigned int iforce;
+ volatile unsigned int iclear;
+ volatile unsigned int mstatus;
+ volatile unsigned int notused[11];
+ volatile unsigned int cpu_mask[16];
+ volatile unsigned int cpu_force[16];
+} ambapp_dev_irqmp;
+
+#endif
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