clk: stm32mp1: Add VREF clock gating

Add VREF clock gating, that may be used by STM32 VREFBUF regulator.

Signed-off-by: Fabrice Gasnier <fabrice.gasnier@st.com>
Signed-off-by: Patrice Chotard <patrice.chotard@st.com>

diff --git a/drivers/clk/clk_stm32mp1.c b/drivers/clk/clk_stm32mp1.c
index ed32585eb02109c24637c52963ef864981fbc65d..1a77eba39cbb430a99fcad34b6768dcccfe4bf96 100644 (file)
--- a/drivers/clk/clk_stm32mp1.c
+++ b/drivers/clk/clk_stm32mp1.c
@@ -100,6 +100,7 @@
 #define RCC_USBCKSELR          0x91C
 #define RCC_MP_APB1ENSETR      0xA00
 #define RCC_MP_APB2ENSETR      0XA08
+#define RCC_MP_APB3ENSETR      0xA10
 #define RCC_MP_AHB2ENSETR      0xA18
 #define RCC_MP_AHB4ENSETR      0xA28
 
@@ -508,6 +509,8 @@ static const struct stm32mp1_clk_gate stm32mp1_clk_gate[] = {
 
        STM32MP1_CLK_SET_CLR(RCC_MP_APB2ENSETR, 13, USART6_K, _UART6_SEL),
 
+       STM32MP1_CLK_SET_CLR_F(RCC_MP_APB3ENSETR, 13, VREF, _PCLK3),
+
        STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 8, DDRPERFM, _UNKNOWN_SEL),
        STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 15, IWDG2, _UNKNOWN_SEL),
        STM32MP1_CLK_SET_CLR(RCC_MP_APB4ENSETR, 16, USBPHY_K, _USBPHY_SEL),