Revert "armv8: enable HAFDBS for other ELx when FEAT_HAFDBS is present"

This reverts commit c1da6fdb5c239b432440721772d993e63cfdeb20. This is
part of a series trying to make use of the arm64 hardware features for
tracking dirty pages. Unfortunately this series causes problems for the
AC5/AC5X SoCs. Having exhausted other options the consensus seems to be
reverting this series is the best course of action.

Signed-off-by: Chris Packham <judge.packham@gmail.com>

diff --git a/arch/arm/cpu/armv8/cache_v8.c b/arch/arm/cpu/armv8/cache_v8.c
index cb1131a0480e788c4d85fe2c24df09713c8f05b0..4c6a1b1d6c5ee74f03fc39da7ca2f8dd53617cd0 100644 (file)
--- a/arch/arm/cpu/armv8/cache_v8.c
+++ b/arch/arm/cpu/armv8/cache_v8.c
@@ -94,15 +94,11 @@ u64 get_tcr(u64 *pips, u64 *pva_bits)
        if (el == 1) {
                tcr = TCR_EL1_RSVD | (ips << 32) | TCR_EPD1_DISABLE;
                if (gd->arch.has_hafdbs)
-                       tcr |= TCR_EL1_HA | TCR_EL1_HD;
+                       tcr |= TCR_HA | TCR_HD;
        } else if (el == 2) {
                tcr = TCR_EL2_RSVD | (ips << 16);
-               if (gd->arch.has_hafdbs)
-                       tcr |= TCR_EL2_HA | TCR_EL2_HD;
        } else {
                tcr = TCR_EL3_RSVD | (ips << 16);
-               if (gd->arch.has_hafdbs)
-                       tcr |= TCR_EL3_HA | TCR_EL3_HD;
        }
 
        /* PTWs cacheable, inner/outer WBWA and inner shareable */

diff --git a/arch/arm/include/asm/armv8/mmu.h b/arch/arm/include/asm/armv8/mmu.h
index 4f0adb07325ffbb7a42080184b98d2f9ccf7a9f7..27658e563951cabf9182a5f76d3194b16609a343 100644 (file)
--- a/arch/arm/include/asm/armv8/mmu.h
+++ b/arch/arm/include/asm/armv8/mmu.h
@@ -102,14 +102,8 @@
 #define TCR_TG0_16K            (2 << 14)
 #define TCR_EPD1_DISABLE       (1 << 23)
 
-#define TCR_EL1_HA             BIT(39)
-#define TCR_EL1_HD             BIT(40)
-
-#define TCR_EL2_HA             BIT(21)
-#define TCR_EL2_HD             BIT(22)
-
-#define TCR_EL3_HA             BIT(21)
-#define TCR_EL3_HD             BIT(22)
+#define TCR_HA                 BIT(39)
+#define TCR_HD                 BIT(40)
 
 #define TCR_EL1_RSVD           (1U << 31)
 #define TCR_EL2_RSVD           (1U << 31 | 1 << 23)