riscv: cpu: Add callback to init each core

Add a callback harts_early_init() to start.S to allow different riscv
hart perform setup code for each hart as early as possible. Since all
the harts enter the callback, they must be able to run the same
setup.

Signed-off-by: Green Wan <green.wan@sifive.com>
Reviewed-by: Rick Chen <rick@andestech.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

diff --git a/arch/riscv/cpu/cpu.c b/arch/riscv/cpu/cpu.c
index 85592f5bee2c67c1251e7e0d0434003dcaa48c8f..296e458db4fe77f93ac9bb7318f95288e65589de 100644 (file)
--- a/arch/riscv/cpu/cpu.c
+++ b/arch/riscv/cpu/cpu.c
@@ -140,3 +140,14 @@ int arch_early_init_r(void)
 {
        return riscv_cpu_probe();
 }
+
+/**
+ * harts_early_init() - A callback function called by start.S to configure
+ * feature settings of each hart.
+ *
+ * In a multi-core system, memory access shall be careful here, it shall
+ * take care of race conditions.
+ */
+__weak void harts_early_init(void)
+{
+}

diff --git a/arch/riscv/cpu/start.S b/arch/riscv/cpu/start.S
index 8589509e012eb737d0ec1ba9d5eccf329ad275b8..308b0a97a58fa0ad81af39c9a9aa39c59ce849a6 100644 (file)
--- a/arch/riscv/cpu/start.S
+++ b/arch/riscv/cpu/start.S
@@ -117,6 +117,10 @@ call_board_init_f_0:
        mv      sp, a0
 #endif
 
+       /* Configure proprietary settings and customized CSRs of harts */
+call_harts_early_init:
+       jal     harts_early_init
+
 #ifndef CONFIG_XIP
        /*
         * Pick hart to initialize global data and run U-Boot. The other harts