ARM: imx: vining2000: Repair PCIe support

Ever since the conversion to DM PCI, the board was missing the PCIe DT
nodes, hence the PCI did not really work. Fill in the DT nodes and add
missing PCIe device reset.

Moreover, bring the PCIe power domain up before booting Linux. This is
mandatory to keep old broken vendor kernels working, as they do not do
so and depend on the bootloader to bring the power domain up.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Silvio Fricke <silvio.fricke@softing.com>
Cc: Stefano Babic <sbabic@denx.de>

diff --git a/arch/arm/dts/imx6sx-softing-vining-2000.dts b/arch/arm/dts/imx6sx-softing-vining-2000.dts
index 371890ff6084412c4e9c4495063b319aaab59682..78dd5755a379b216ed6eab87779b22e39a65664c 100644 (file)
--- a/arch/arm/dts/imx6sx-softing-vining-2000.dts
+++ b/arch/arm/dts/imx6sx-softing-vining-2000.dts
@@ -270,6 +270,17 @@
        status = "okay";
 };
 
+&reg_pcie {
+       regulator-always-on;
+};
+
+&pcie {
+       pinctrl-names = "default";
+       pinctrl-0 = <&pinctrl_pcie>;
+       reset-gpio = <&gpio4 6 GPIO_ACTIVE_HIGH>;
+       status = "okay";
+};
+
 &iomuxc {
        pinctrl-names = "default";
        pinctrl-0 = <&pinctrl_gpios>;
@@ -360,6 +371,12 @@
                >;
        };
 
+       pinctrl_pcie: pciegrp {
+               fsl,pins = <
+                       MX6SX_PAD_NAND_DATA02__GPIO4_IO_6       0x10b0
+               >;
+       };
+
        pinctrl_pwm1: pwm1grp-1 {
                fsl,pins = <
                        /* blue LED */

diff --git a/board/softing/vining_2000/vining_2000.c b/board/softing/vining_2000/vining_2000.c
index b6f1415bb5acd5709f8da988b5d827b59b60d385..fe47c365a12cc29594910dab2151d2f9eda807a5 100644 (file)
--- a/board/softing/vining_2000/vining_2000.c
+++ b/board/softing/vining_2000/vining_2000.c
@@ -406,6 +406,19 @@ int checkboard(void)
        return 0;
 }
 
+#define PCIE_PHY_PUP_REQ               BIT(7)
+
+void board_preboot_os(void)
+{
+       struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR;
+       struct gpc *gpc_regs = (struct gpc *)GPC_BASE_ADDR;
+
+       /* Bring the PCI power domain up, so that old vendorkernel works. */
+       setbits_le32(&iomuxc_regs->gpr[12], IOMUXC_GPR12_TEST_POWERDOWN);
+       setbits_le32(&iomuxc_regs->gpr[5], IOMUXC_GPR5_PCIE_BTNRST);
+       setbits_le32(&gpc_regs->cntr, PCIE_PHY_PUP_REQ);
+}
+
 #ifdef CONFIG_SPL_BUILD
 #include <linux/libfdt.h>
 #include <spl.h>
@@ -413,6 +426,10 @@ int checkboard(void)
 
 static struct fsl_esdhc_cfg usdhc_cfg = { USDHC4_BASE_ADDR };
 
+static iomux_v3_cfg_t const pcie_pads[] = {
+       MX6_PAD_NAND_DATA02__GPIO4_IO_6 | MUX_PAD_CTRL(GPIO_PAD_CTRL),
+};
+
 static iomux_v3_cfg_t const uart_pads[] = {
        MX6_PAD_GPIO1_IO04__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL),
        MX6_PAD_GPIO1_IO05__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL),
@@ -431,6 +448,11 @@ static iomux_v3_cfg_t const usdhc4_pads[] = {
        MX6_PAD_SD4_DATA7__USDHC4_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL),
 };
 
+static void vining2000_spl_setup_iomux_pcie(void)
+{
+       imx_iomux_v3_setup_multiple_pads(pcie_pads, ARRAY_SIZE(pcie_pads));
+}
+
 static void vining2000_spl_setup_iomux_uart(void)
 {
        imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads));
@@ -574,11 +596,17 @@ void board_init_f(ulong dummy)
        ccgr_init();
 
        /* iomux setup */
+       vining2000_spl_setup_iomux_pcie();
        vining2000_spl_setup_iomux_uart();
 
        /* setup GP timer */
        timer_init();
 
+       /* reset the PCIe device */
+       gpio_set_value(IMX_GPIO_NR(4, 6), 1);
+       udelay(50);
+       gpio_set_value(IMX_GPIO_NR(4, 6), 0);
+
        /* UART clocks enabled and gd valid - init serial console */
        preloader_console_init();