x86: apl: Drop the I2C config in FSP-S

This config is not actually used here and in U-Boot it seems better to set
this using the device tree for each individual controller. The monolithic
config of the FSP-S is only necessary if the FSP is actually configuring
something, but here it is not.

The FSP-S does enable/disable the various I2C ports. It might be nice to
handle this using the okay/disabled property of each port, but that can be
considered later.

Signed-off-by: Simon Glass <sjg@chromium.org>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>

diff --git a/arch/x86/cpu/apollolake/fsp_s.c b/arch/x86/cpu/apollolake/fsp_s.c
index 9804227f80bd5f174f0d74019c9772528ac58453..f8fa4dec8f718352954b66efd31944c9338e95b2 100644 (file)
--- a/arch/x86/cpu/apollolake/fsp_s.c
+++ b/arch/x86/cpu/apollolake/fsp_s.c
@@ -24,7 +24,6 @@
 #define HIDE_BIT               BIT(0)
 
 #define INTEL_GSPI_MAX         3
-#define INTEL_I2C_DEV_MAX      8
 #define MAX_USB2_PORTS         8
 
 enum {
@@ -32,36 +31,6 @@ enum {
        CHIPSET_LOCKDOWN_COREBOOT, /* coreboot handles locking */
 };
 
-enum i2c_speed {
-       I2C_SPEED_STANDARD      = 100000,
-       I2C_SPEED_FAST          = 400000,
-       I2C_SPEED_FAST_PLUS     = 1000000,
-       I2C_SPEED_HIGH          = 3400000,
-       I2C_SPEED_FAST_ULTRA    = 5000000,
-};
-
-/*
- * Timing values are in units of clock period, with the clock speed
- * provided by the SOC
- *
- * TODO(sjg@chromium.org): Connect this up to the I2C driver
- */
-struct dw_i2c_speed_config {
-       enum i2c_speed speed;
-       /* SCL high and low period count */
-       u16 scl_lcnt;
-       u16 scl_hcnt;
-       /*
-        * SDA hold time should be 300ns in standard and fast modes
-        * and long enough for deterministic logic level change in
-        * fast-plus and high speed modes.
-        *
-        *  [15:0] SDA TX Hold Time
-        * [23:16] SDA RX Hold Time
-        */
-       u32 sda_hold;
-};
-
 /* Serial IRQ control. SERIRQ_QUIET is the default (0) */
 enum serirq_mode {
        SERIRQ_QUIET,
@@ -69,32 +38,6 @@ enum serirq_mode {
        SERIRQ_OFF,
 };
 
-/*
- * This I2C controller has support for 3 independent speed configs but can
- * support both FAST_PLUS and HIGH speeds through the same set of speed
- * config registers.  These are treated separately so the speed config values
- * can be provided via ACPI to the OS.
- */
-#define DW_I2C_SPEED_CONFIG_COUNT      4
-
-struct dw_i2c_bus_config {
-       /* Bus should be enabled in TPL with temporary base */
-       int early_init;
-       /* Bus speed in Hz, default is I2C_SPEED_FAST (400 KHz) */
-       enum i2c_speed speed;
-       /*
-        * If rise_time_ns is non-zero the calculations for lcnt and hcnt
-        * registers take into account the times of the bus. However, if
-        * there is a match in speed_config those register values take
-        * precedence
-        */
-       int rise_time_ns;
-       int fall_time_ns;
-       int data_hold_time_ns;
-       /* Specific bus speed configuration */
-       struct dw_i2c_speed_config speed_config[DW_I2C_SPEED_CONFIG_COUNT];
-};
-
 struct gspi_cfg {
        /* Bus speed in MHz */
        u32 speed_mhz;
@@ -110,7 +53,6 @@ struct gspi_cfg {
 struct soc_intel_common_config {
        int chipset_lockdown;
        struct gspi_cfg gspi[INTEL_GSPI_MAX];
-       struct dw_i2c_bus_config i2c[INTEL_I2C_DEV_MAX];
 };
 
 enum pnp_settings {