SoC Control 1 Register (offset 0x18204) is already defined by macro
SOC_CONTROL_REG1.
Use macro SOC_CONTROL_REG1 instead of macro SOC_CTRL_REG in ctrl_pex.c
code and remove the other definition.
Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>
reg_write(PEX_CAPABILITIES_REG(pex_idx), tmp);
}
- tmp = reg_read(SOC_CTRL_REG);
+ tmp = reg_read(SOC_CONTROL_REG1);
tmp &= ~0x03;
for (idx = 0; idx < count; idx++) {
}
}
- reg_write(SOC_CTRL_REG, tmp);
+ reg_write(SOC_CONTROL_REG1, tmp);
/* Support gen1/gen2 */
DEBUG_INIT_FULL_S("Support gen1/gen2\n");
/* PCI Express Control and Status Registers */
#define MAX_PEX_BUSSES 256
-#define MISC_REGS_OFFSET 0x18200
-#define MV_MISC_REGS_BASE MISC_REGS_OFFSET
-#define SOC_CTRL_REG (MV_MISC_REGS_BASE + 0x4)
-
#define PEX_IF_REGS_OFFSET(if) ((if) > 0 ? \
(0x40000 + ((if) - 1) * 0x4000) : \
0x80000)