T1023RDB is a Freescale Reference Design Board that hosts the T1023 SoC.
T1023RDB board Overview
-----------------------
- T1023 SoC integrating two 64-bit e5500 cores up to 1.4GHz
- CoreNet fabric supporting coherent and noncoherent transactions with
prioritization and bandwidth allocation
- Memory: 2GB Micron MT40A512M8HX unbuffered 32-bit fixed DDR4 without ECC
- Accelerator: DPAA components consist of FMan, BMan, QMan, DCE and SEC
- Ethernet interfaces:
- one 1G RGMII port on-board(RTL8211F PHY)
- one 1G SGMII port on-board(RTL8211F PHY)
- one 2.5G SGMII port on-board(AQR105 PHY)
- PCIe: Two Mini-PCIe connectors on-board.
- SerDes: 4 lanes up to 10.3125GHz
- NOR: 128MB S29GL01GS110TFIV10 Spansion NOR Flash
- NAND: 512MB S34MS04G200BFI000 Spansion NAND Flash
- eSPI: 64MB S25FL512SAGMFI010 Spansion SPI flash.
- USB: one Type-A USB 2.0 port with internal PHY
- eSDHC: support SD/MMC card and eMMC on-board
- 256Kbit M24256 I2C EEPROM
- RTC: Real-time clock DS1339 on I2C bus
- UART: one serial port on-board with RJ45 connector
- Debugging: JTAG/COP for T1023 debugging
As well updated T1024RDB to add T1023RDB.
Signed-off-by: Shengzhou Liu <Shengzhou.Liu@freescale.com>
[York Sun: fix defconfig files]
Reviewed-by: York Sun <yorksun@freescale.com>
F: configs/T1024RDB_SDCARD_defconfig
F: configs/T1024RDB_SPIFLASH_defconfig
F: configs/T1024RDB_SECURE_BOOT_defconfig
+F: configs/T1023RDB_defconfig
+F: configs/T1023RDB_NAND_defconfig
+F: configs/T1023RDB_SDCARD_defconfig
+F: configs/T1023RDB_SPIFLASH_defconfig
+F: configs/T1023RDB_SECURE_BOOT_defconfig
obj-y += spl.o
else
obj-y += t102xrdb.o
-obj-y += cpld.o
+obj-$(CONFIG_T1024RDB) += cpld.o
obj-y += eth_t102xrdb.o
obj-$(CONFIG_PCI) += pci.o
endif
- Four I2C ports
+T1023RDB board Overview
+-----------------------
+- T1023 SoC integrating two 64-bit e5500 cores up to 1.4GHz
+- CoreNet fabric supporting coherent and noncoherent transactions with
+ prioritization and bandwidth allocation
+- SDRAM memory: 2GB Micron MT40A512M8HX unbuffered 32-bit DDR4 w/o ECC
+- Accelerator: DPAA components consist of FMan, BMan, QMan, DCE and SEC
+- Ethernet interfaces:
+ - one 1G RGMII port on-board(RTL8211FS PHY)
+ - one 1G SGMII port on-board(RTL8211FS PHY)
+ - one 2.5G SGMII port on-board(AQR105 PHY)
+- PCIe: Two Mini-PCIe connectors on-board.
+- SerDes: 4 lanes up to 10.3125GHz
+- NOR: 128MB S29GL01GS110TFIV10 Spansion NOR Flash
+- NAND: 512MB S34MS04G200BFI000 Spansion NAND Flash
+- eSPI: 64MB S25FL512SAGMFI010 Spansion SPI flash.
+- USB: one Type-A USB 2.0 port with internal PHY
+- eSDHC: support SD/MMC and eMMC card
+- 256Kbit M24256 I2C EEPROM
+- RTC: Real-time clock DS1339U on I2C bus
+- UART: one serial port on-board with RJ45 connector
+- Debugging: JTAG/COP for T1023 debugging
+
+
Memory map on T1024RDB
----------------------
Start Address End Address Description Size
0x0_0000_0000 0x0_ffff_ffff DDR 4GB
-128MB NOR Flash memory Map
---------------------------
+128MB NOR Flash Memory Layout
+-----------------------------
Start Address End Address Definition Max size
0xEFF40000 0xEFFFFFFF u-boot (current bank) 768KB
0xEFF20000 0xEFF3FFFF u-boot env (current bank) 128KB
0xEFF00000 0xEFF1FFFF FMAN Ucode (current bank) 128KB
0xEFE00000 0xEFE3FFFF QE firmware (current bank) 256KB
-0xED300000 0xEFEFFFFF rootfs (alt bank) 44MB
+0xED300000 0xEFDFFFFF rootfs (alt bank) 44MB
+0xED000000 0xED2FFFFF Guest image #3 (alternate bank) 3MB
+0xECD00000 0xECFFFFFF Guest image #2 (alternate bank) 3MB
+0xECA00000 0xECCFFFFF Guest image #1 (alternate bank) 3MB
+0xEC900000 0xEC9FFFFF HV config device tree(alt bank) 1MB
0xEC800000 0xEC8FFFFF Hardware device tree (alt bank) 1MB
-0xEC020000 0xEC7FFFFF Linux.uImage (alt bank) 7MB + 875KB
+0xEC700000 0xEC7FFFFF HV.uImage (alternate bank) 1MB
+0xEC020000 0xEC6FFFFF Linux.uImage (alt bank) ~7MB
0xEC000000 0xEC01FFFF RCW (alt bank) 128KB
0xEBF40000 0xEBFFFFFF u-boot (alt bank) 768KB
0xEBF20000 0xEBF3FFFF u-boot env (alt bank) 128KB
0xEBF00000 0xEBF1FFFF FMAN ucode (alt bank) 128KB
0xEBE00000 0xEBE3FFFF QE firmware (alt bank) 256KB
-0xE9300000 0xEBEFFFFF rootfs (current bank) 44MB
+0xE9300000 0xEBDFFFFF rootfs (current bank) 44MB
+0xE9000000 0xE92FFFFF Guest image #3 (current bank) 3MB
+0xE8D00000 0xE8FFFFFF Guest image #2 (current bank) 3MB
+0xE8A00000 0xE8CFFFFF Guest image #1 (current bank) 3MB
+0xE8900000 0xE89FFFFF HV config device tree(cur bank) 1MB
0xE8800000 0xE88FFFFF Hardware device tree (cur bank) 1MB
-0xE8020000 0xE86FFFFF Linux.uImage (current bank) 7MB + 875KB
+0xE8700000 0xE87FFFFF HV.uImage (current bank) 1MB
+0xE8020000 0xE86FFFFF Linux.uImage (current bank) ~7MB
0xE8000000 0xE801FFFF RCW (current bank) 128KB
-T1024 Clock frequency
----------------------
+T1024/T1023 Clock frequency
+---------------------------
BIN Core DDR Platform FMan
Bin1: 1400MHz 1600MT/s 400MHz 700MHz
Bin2: 1200MHz 1600MT/s 400MHz 600MHz
b. program u-boot.bin image to NOR flash
=> tftp 1000000 u-boot.bin
=> pro off all;era eff40000 efffffff;cp.b 1000000 eff40000 $filesize
- set SW1[1:8] = '00010011', SW2[1] = '1', SW3[4] = '0' for NOR boot
+ on T1024RDB:
+ set SW1[1:8] = '00010011', SW2[1] = '1', SW3[4] = '0' for NOR boot
+ on T1023RDB:
+ set SW1[1:8] = '00010110', SW2[1] = '0', SW3[4] = '0' for NOR boot
Switching between default bank0 and alternate bank4 on NOR flash
To change boot source to vbank4:
- via software: run command 'cpld reset altbank' in u-boot.
- via DIP-switch: set SW3[5:7] = '100'
+ on T1024RDB:
+ via software: run command 'cpld reset altbank' in u-boot.
+ via DIP-switch: set SW3[5:7] = '100'
+ on T1023RDB:
+ via software: run command 'gpio vbank4' in u-boot.
+ via DIP-switch: set SW3[5:7] = '100'
To change boot source to vbank0:
- via software: run command 'cpld reset' in u-boot.
- via DIP-Switch: set SW3[5:7] = '000'
+ on T1024RDB:
+ via software: run command 'cpld reset' in u-boot.
+ via DIP-Switch: set SW3[5:7] = '000'
+ on T1023RDB:
+ via software: run command 'gpio vbank0' in u-boot.
+ via DIP-switch: set SW3[5:7] = '000'
2. NAND Boot:
a. build PBL image for NAND boot
b. program u-boot-with-spl-pbl.bin to SPI flash
=> tftp 1000000 u-boot-with-spl-pbl.bin
=> sf probe 0
- => sf erase 0 f0000
+ => sf erase 0 100000
=> sf write 1000000 0 $filesize
+ => tftp 1000000 fsl_fman_ucode_t1024_xx.bin
+ => sf erase 100000 100000
+ => sf write 1000000 110000 20000
set SW1[1:8] = '00100010', SW2[1] ='1' for SPI boot
4. SD Boot:
0x200000 0x27FFFF QE Firmware 512KB(1 block)
+NAND Flash memory Map on T1023RDB
+----------------------------------------------------
+Start End Definition Size
+0x000000 0x0FFFFF u-boot 1MB
+0x100000 0x15FFFF u-boot env 8KB
+0x160000 0x17FFFF FMAN Ucode 128KB
+
+
SD Card memory Map on T1024RDB
----------------------------------------------------
Block #blocks Definition Size
0x008 2048 u-boot img 1MB
0x800 0016 u-boot env 8KB
0x820 0256 FMAN Ucode 128KB
-0x920 0256 QE Firmware 128KB
+0x920 0256 QE Firmware 128KB(only T1024RDB)
-SPI Flash memory Map on T1024RDB
+64MB SPI Flash memory Map on T102xRDB
----------------------------------------------------
Start End Definition Size
0x000000 0x0FFFFF u-boot img 1MB
0x100000 0x101FFF u-boot env 8KB
0x110000 0x12FFFF FMAN Ucode 128KB
-0x130000 0x14FFFF QE Firmware 128KB
+0x130000 0x14FFFF QE Firmware 128KB(only T1024RDB)
+0x300000 0x3FFFFF device tree 128KB
+0x400000 0x9FFFFF Linux kernel 6MB
+0xa00000 0x3FFFFFF rootfs 54MB
-For more details, please refer to T1024RDB Reference Manual and access
-website www.freescale.com and Freescale QorIQ SDK Infocenter document.
+For more details, please refer to T1024RDB Reference Manual
+and Freescale QorIQ SDK Infocenter document.
/* for DDR bus 32bit test on T1024 */
popts->data_bus_width = DDR_DATA_BUS_WIDTH_32;
#endif
+
+#ifdef CONFIG_T1023RDB
+ popts->wrlvl_ctl_2 = 0x07070606;
+ popts->half_strength_driver_enable = 1;
+#endif
}
+#ifdef CONFIG_SYS_DDR_RAW_TIMING
+/* 2GB discrete DDR4 MT40A512M8HX on T1023RDB */
+dimm_params_t ddr_raw_timing = {
+ .n_ranks = 1,
+ .rank_density = 0x80000000,
+ .capacity = 0x80000000,
+ .primary_sdram_width = 32,
+ .ec_sdram_width = 8,
+ .registered_dimm = 0,
+ .mirrored_dimm = 0,
+ .n_row_addr = 15,
+ .n_col_addr = 10,
+ .bank_addr_bits = 2,
+ .bank_group_bits = 2,
+ .edc_config = 0,
+ .burst_lengths_bitmask = 0x0c,
+ .tckmin_x_ps = 938,
+ .tckmax_ps = 1500,
+ .caslat_x = 0x000DFA00,
+ .taa_ps = 13500,
+ .trcd_ps = 13500,
+ .trp_ps = 13500,
+ .tras_ps = 33000,
+ .trc_ps = 46500,
+ .trfc1_ps = 260000,
+ .trfc2_ps = 160000,
+ .trfc4_ps = 110000,
+ .tfaw_ps = 25000,
+ .trrds_ps = 3700,
+ .trrdl_ps = 5300,
+ .tccdl_ps = 5355,
+ .refresh_rate_ps = 7800000,
+ .dq_mapping[0] = 0x0,
+ .dq_mapping[1] = 0x0,
+ .dq_mapping[2] = 0x0,
+ .dq_mapping[3] = 0x0,
+ .dq_mapping[4] = 0x0,
+ .dq_mapping[5] = 0x0,
+ .dq_mapping[6] = 0x0,
+ .dq_mapping[7] = 0x0,
+ .dq_mapping[8] = 0x0,
+ .dq_mapping[9] = 0x0,
+ .dq_mapping[10] = 0x0,
+ .dq_mapping[11] = 0x0,
+ .dq_mapping[12] = 0x0,
+ .dq_mapping[13] = 0x0,
+ .dq_mapping[14] = 0x0,
+ .dq_mapping[15] = 0x0,
+ .dq_mapping[16] = 0x0,
+ .dq_mapping[17] = 0x0,
+ .dq_mapping_ors = 1,
+};
+
+int fsl_ddr_get_dimm_params(dimm_params_t *pdimm,
+ unsigned int controller_number,
+ unsigned int dimm_number)
+{
+ const char dimm_model[] = "Fixed DDR4 on board";
+
+ if (((controller_number == 0) && (dimm_number == 0)) ||
+ ((controller_number == 1) && (dimm_number == 0))) {
+ memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t));
+ memset(pdimm->mpart, 0, sizeof(pdimm->mpart));
+ memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1);
+ }
+
+ return 0;
+}
+#endif
+
#if defined(CONFIG_DEEP_SLEEP)
void board_mem_sleep_setup(void)
{
phys_size_t dram_size;
#if defined(CONFIG_SPL_BUILD) || !defined(CONFIG_RAMBOOT_PBL)
+#ifndef CONFIG_SYS_DDR_RAW_TIMING
puts("Initializing....using SPD\n");
-
+#endif
dram_size = fsl_ddr_sdram();
dram_size = setup_ddr_tlbs(dram_size / 0x100000);
dram_size *= 0x100000;
/*
* Copyright 2014 Freescale Semiconductor, Inc.
*
+ * Shengzhou Liu <Shengzhou.Liu@freescale.com>
+ *
* SPDX-License-Identifier: GPL-2.0+
*/
fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY1_ADDR);
switch (srds_s1) {
+#ifdef CONFIG_T1024RDB
case 0x95:
/* set the on-board RGMII2 PHY */
fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY2_ADDR);
/* set 10G XFI with Aquantia AQR105 PHY */
fm_info_set_phy_address(FM1_10GEC1, FM1_10GEC1_PHY_ADDR);
break;
+#endif
+ case 0x6a:
+ case 0x6b:
case 0x77:
case 0x135:
/* set the on-board 2.5G SGMII AQR105 PHY */
- fm_info_set_phy_address(FM1_DTSEC3, SGMII_PHY1_ADDR);
+ fm_info_set_phy_address(FM1_DTSEC3, SGMII_AQR_PHY_ADDR);
+#ifdef CONFIG_T1023RDB
+ /* set the on-board 1G SGMII RTL8211F PHY */
+ fm_info_set_phy_address(FM1_DTSEC1, SGMII_RTK_PHY_ADDR);
+#endif
break;
default:
printf("SerDes protocol 0x%x is not supported on T102xRDB\n",
dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
fm_info_set_mdio(i, dev);
break;
+ case PHY_INTERFACE_MODE_SGMII:
+#if defined(CONFIG_T1023RDB)
+ dev = miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME);
+#elif defined(CONFIG_T1024RDB)
+ dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
+#endif
+ fm_info_set_mdio(i, dev);
+ break;
case PHY_INTERFACE_MODE_SGMII_2500:
dev = miiphy_get_dev_by_name(DEFAULT_FM_TGEC_MDIO_NAME);
fm_info_set_mdio(i, dev);
void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
enum fm_port port, int offset)
{
- if ((fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) &&
- (port == FM1_DTSEC3)) {
+#if defined(CONFIG_T1024RDB)
+ if (((fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) ||
+ (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII)) &&
+ (port == FM1_DTSEC3)) {
fdt_set_phy_handle(fdt, compat, addr, "sg_2500_aqr105_phy4");
fdt_setprop(fdt, offset, "phy-connection-type",
"sgmii-2500", 10);
fdt_status_disabled_by_alias(fdt, "xg_aqr105_phy3");
}
+#endif
}
void fdt_fixup_board_enet(void *fdt)
--- /dev/null
+#PBL preamble and RCW header for T1023RDB
+aa55aa55 010e0100
+#SerDes Protocol: 0x77
+#Core/DDR: 1400Mhz/1600MT/s with single source clock
+0810000e 00000000 00000000 00000000
+3b800003 00000012 e8104000 21000000
+00000000 00000000 00000000 00020800
+00000130 04020200 00000000 00000006
#include <asm/fsl_liodn.h>
#include <fm_eth.h>
#include "t102xrdb.h"
+#ifdef CONFIG_T1024RDB
#include "cpld.h"
+#endif
#include "../common/sleep.h"
DECLARE_GLOBAL_DATA_PTR;
+#ifdef CONFIG_T1023RDB
+enum {
+ GPIO1_SD_SEL = 0x00020000, /* GPIO1_14, 0: EMMC, 1:SD/MMC */
+ GPIO1_EMMC_SEL,
+ GPIO1_VBANK0,
+ GPIO1_VBANK4 = 0x00008000, /* GPIO1_16/20/22, 100:vBank4 */
+ GPIO1_VBANK_MASK = 0x00008a00,
+ GPIO1_DIR_OUTPUT = 0x00028a00,
+ GPIO1_GET_VAL,
+};
+#endif
+
int checkboard(void)
{
struct cpu_type *cpu = gd->arch.cpu;
srds_s1 >>= FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT;
printf("Board: %sRDB, ", cpu->name);
- printf("Board rev: 0x%02x CPLD ver: 0x%02x, boot from ",
+#ifdef CONFIG_T1024RDB
+ printf("Board rev: 0x%02x CPLD ver: 0x%02x, ",
CPLD_READ(hw_ver), CPLD_READ(sw_ver));
+#endif
+ printf("boot from ");
#ifdef CONFIG_SDCARD
puts("SD/MMC\n");
#elif CONFIG_SPIFLASH
puts("SPI\n");
-#else
+#elif defined(CONFIG_T1024RDB)
u8 reg;
reg = CPLD_READ(flash_csr);
reg = ((reg & CPLD_LBMAP_MASK) >> CPLD_LBMAP_SHIFT);
printf("NOR vBank%d\n", reg);
}
+#elif defined(CONFIG_T1023RDB)
+#ifdef CONFIG_NAND
+ puts("NAND\n");
+#else
+ printf("NOR vBank%d\n", (t1023rdb_gpio_ctrl(GPIO1_GET_VAL) &
+ GPIO1_VBANK4) >> 15 ? 4 : 0);
+#endif
#endif
puts("SERDES Reference Clocks:\n");
if (srds_s1 == 0x95)
printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[2], freq[0]);
else
- printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[0], freq[0]);
+ printf("SD1_CLK1=%s, SD1_CLK2=%s\n", freq[0], freq[1]);
return 0;
}
+#ifdef CONFIG_T1024RDB
static void board_mux_lane(void)
{
ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
}
CPLD_WRITE(boot_override, CPLD_OVERRIDE_MUX_EN);
}
+#endif
int board_early_init_f(void)
{
#ifdef CONFIG_SYS_DPAA_QBMAN
setup_portals();
#endif
+#ifdef CONFIG_T1024RDB
board_mux_lane();
+#endif
return 0;
}
return 0;
}
+
+
+#ifdef CONFIG_T1023RDB
+static u32 t1023rdb_gpio_ctrl(u32 ctrl_type)
+{
+ ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR);
+ u32 gpioval;
+
+ setbits_be32(&pgpio->gpdir, GPIO1_DIR_OUTPUT);
+ gpioval = in_be32(&pgpio->gpdat);
+
+ switch (ctrl_type) {
+ case GPIO1_SD_SEL:
+ gpioval |= GPIO1_SD_SEL;
+ break;
+ case GPIO1_EMMC_SEL:
+ gpioval &= ~GPIO1_SD_SEL;
+ break;
+ case GPIO1_VBANK0:
+ gpioval &= ~GPIO1_VBANK_MASK;
+ break;
+ case GPIO1_VBANK4:
+ gpioval &= ~GPIO1_VBANK_MASK;
+ gpioval |= GPIO1_VBANK4;
+ break;
+ case GPIO1_GET_VAL:
+ return gpioval;
+ default:
+ break;
+ }
+ out_be32(&pgpio->gpdat, gpioval);
+
+ return 0;
+}
+
+static int gpio_cmd(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ if (argc < 2)
+ return CMD_RET_USAGE;
+ if (!strcmp(argv[1], "vbank0"))
+ t1023rdb_gpio_ctrl(GPIO1_VBANK0);
+ else if (!strcmp(argv[1], "vbank4"))
+ t1023rdb_gpio_ctrl(GPIO1_VBANK4);
+ else if (!strcmp(argv[1], "sd"))
+ t1023rdb_gpio_ctrl(GPIO1_SD_SEL);
+ else if (!strcmp(argv[1], "EMMC"))
+ t1023rdb_gpio_ctrl(GPIO1_EMMC_SEL);
+ else
+ return CMD_RET_USAGE;
+ return 0;
+}
+
+U_BOOT_CMD(
+ gpio, 2, 0, gpio_cmd,
+ "for vbank0/vbank4/SD/eMMC switch control in runtime",
+ "command (e.g. gpio vbank4)"
+);
+#endif
void fdt_fixup_board_enet(void *blob);
void pci_of_setup(void *blob, bd_t *bd);
-
+#ifdef CONFIG_T1023RDB
+static u32 t1023rdb_gpio_ctrl(u32 ctrl_type);
+#endif
#endif
--- /dev/null
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T102XRDB=y
--- /dev/null
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T102XRDB=y
--- /dev/null
+CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB,SECURE_BOOT"
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T102XRDB=y
--- /dev/null
+CONFIG_SPL=y
+CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T102XRDB=y
--- /dev/null
+CONFIG_SYS_EXTRA_OPTIONS="PPC_T1023,T1023RDB"
+CONFIG_PPC=y
+CONFIG_MPC85xx=y
+CONFIG_TARGET_T102XRDB=y
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
+CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB,RAMBOOT_PBL,SPL_FSL_PBL,NAND"
CONFIG_PPC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T102XRDB=y
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
+CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB,RAMBOOT_PBL,SPL_FSL_PBL,SDCARD"
CONFIG_PPC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T102XRDB=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,SECURE_BOOT"
+CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB,SECURE_BOOT"
CONFIG_PPC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T102XRDB=y
CONFIG_SPL=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
+CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB,RAMBOOT_PBL,SPL_FSL_PBL,SPIFLASH"
CONFIG_PPC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T102XRDB=y
-CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024"
+CONFIG_SYS_EXTRA_OPTIONS="PPC_T1024,T1024RDB"
CONFIG_PPC=y
CONFIG_MPC85xx=y
CONFIG_TARGET_T102XRDB=y
#ifndef __T1024RDB_H
#define __T1024RDB_H
+#if defined(CONFIG_T1023RDB)
+#ifdef CONFIG_SPL
+#define CONFIG_SYS_NO_FLASH
+#endif
+#endif
+
/* High Level Configuration Options */
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_ENV_OVERWRITE
/* support deep sleep */
+#ifdef CONFIG_PPC_T1024
#define CONFIG_DEEP_SLEEP
+#endif
#if defined(CONFIG_DEEP_SLEEP)
#define CONFIG_SILENT_CONSOLE
#define CONFIG_BOARD_EARLY_INIT_F
#ifdef CONFIG_RAMBOOT_PBL
#define CONFIG_SYS_FSL_PBL_PBI board/freescale/t102xrdb/t1024_pbi.cfg
+#if defined(CONFIG_T1024RDB)
#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1024_rcw.cfg
+#elif defined(CONFIG_T1023RDB)
+#define CONFIG_SYS_FSL_PBL_RCW board/freescale/t102xrdb/t1023_rcw.cfg
+#endif
#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
#define CONFIG_SPL_ENV_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_ENV_SPI_MODE 0
#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
+#if defined(CONFIG_T1024RDB)
#define CONFIG_ENV_SECT_SIZE 0x10000
+#elif defined(CONFIG_T1023RDB)
+#define CONFIG_ENV_SECT_SIZE 0x40000
+#endif
#elif defined(CONFIG_SDCARD)
#define CONFIG_SYS_EXTRA_ENV_RELOC
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_EXTRA_ENV_RELOC
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_SIZE 0x2000
+#if defined(CONFIG_T1024RDB)
#define CONFIG_ENV_OFFSET (2 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_T1023RDB)
+#define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#endif
#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
#define CONFIG_ENV_IS_IN_REMOTE
#define CONFIG_ENV_ADDR 0xffe20000
#endif
#define CONFIG_SYS_CLK_FREQ 100000000
-#define CONFIG_DDR_CLK_FREQ 66660000
+#define CONFIG_DDR_CLK_FREQ 100000000
/*
* These can be toggled for performance analysis, otherwise use default.
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif
+#define CONFIG_CMD_MEMTEST
#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
#define CONFIG_SYS_MEMTEST_END 0x00400000
#define CONFIG_SYS_ALT_MEMTEST
#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
#define CONFIG_DIMM_SLOTS_PER_CTLR 1
#define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
+#define CONFIG_FSL_DDR_INTERACTIVE
+#if defined(CONFIG_T1024RDB)
#define CONFIG_DDR_SPD
#define CONFIG_SYS_FSL_DDR3
-
#define CONFIG_SYS_SPD_BUS_NUM 0
#define SPD_EEPROM_ADDRESS 0x51
-
#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
+#elif defined(CONFIG_T1023RDB)
+#define CONFIG_SYS_FSL_DDR4
+#define CONFIG_SYS_DDR_RAW_TIMING
+#define CONFIG_SYS_SDRAM_SIZE 2048
+#endif
/*
* IFC Definitions
#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
/* NOR Flash Timing Params */
+#if defined(CONFIG_T1024RDB)
#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
+#elif defined(CONFIG_T1023RDB)
+#define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
+ CSOR_NAND_TRHZ_80 | CSOR_NOR_ADM_SHFT_MODE_EN)
+#endif
#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
FTIM0_NOR_TEADC(0x5) | \
FTIM0_NOR_TEAHC(0x5))
#define CONFIG_SYS_FLASH_EMPTY_INFO
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
+#ifdef CONFIG_T1024RDB
/* CPLD on IFC */
#define CONFIG_SYS_CPLD_BASE 0xffdf0000
#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull | CONFIG_SYS_CPLD_BASE)
FTIM2_GPCM_TCH(0x8) | \
FTIM2_GPCM_TWP(0x1f))
#define CONFIG_SYS_CS2_FTIM3 0x0
+#endif
/* NAND Flash on IFC */
#define CONFIG_NAND_FSL_IFC
| CSPR_V)
#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
+#if defined(CONFIG_T1024RDB)
#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
| CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
| CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
| CSOR_NAND_PGS_4K /* Page Size = 4K */ \
| CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
| CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
+#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
+#elif defined(CONFIG_T1023RDB)
+#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_RAL_3 /* RAL 3Bytes */ \
+ | CSOR_NAND_RAL_3 /* RAL 3Bytes */ \
+ | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
+ | CSOR_NAND_SPRZ_128 /* Spare size = 128 */ \
+ | CSOR_NAND_PB(64)) /*Pages Per Block = 64*/
+#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
+#endif
#define CONFIG_SYS_NAND_ONFI_DETECTION
-
/* ONFI NAND Flash mode0 Timing Params */
#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
FTIM0_NAND_TWP(0x18) | \
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_CMD_NAND
-#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
-
#if defined(CONFIG_NAND)
#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
*/
#define CONFIG_FSL_ESPI
#define CONFIG_SPI_FLASH
+#if defined(CONFIG_T1024RDB)
#define CONFIG_SPI_FLASH_STMICRO
+#elif defined(CONFIG_T1023RDB)
+#define CONFIG_SPI_FLASH_SPANSION
+#endif
#define CONFIG_CMD_SF
#define CONFIG_SPI_FLASH_BAR
#define CONFIG_SF_DEFAULT_SPEED 10000000
#define CONFIG_SYS_QE_FW_ADDR (512 * 0x920)
#elif defined(CONFIG_NAND)
#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
+#if defined(CONFIG_T1024RDB)
#define CONFIG_SYS_FMAN_FW_ADDR (3 * CONFIG_SYS_NAND_BLOCK_SIZE)
#define CONFIG_SYS_QE_FW_ADDR (4 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#elif defined(CONFIG_T1023RDB)
+#define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#define CONFIG_SYS_QE_FW_ADDR (12 * CONFIG_SYS_NAND_BLOCK_SIZE)
+#endif
#elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
/*
* Slave has no ucode locally, it can fetch this from remote. When implementing
#define CONFIG_PHYLIB_10G
#define CONFIG_PHY_REALTEK
#define CONFIG_PHY_AQUANTIA
+#if defined(CONFIG_T1024RDB)
#define RGMII_PHY1_ADDR 0x2
#define RGMII_PHY2_ADDR 0x6
-#define SGMII_PHY1_ADDR 0x2
+#define SGMII_AQR_PHY_ADDR 0x2
#define FM1_10GEC1_PHY_ADDR 0x1
+#elif defined(CONFIG_T1023RDB)
+#define RGMII_PHY1_ADDR 0x1
+#define SGMII_RTK_PHY_ADDR 0x3
+#define SGMII_AQR_PHY_ADDR 0x2
+#endif
#endif
#ifdef CONFIG_FMAN_ENET
*/
#define CONFIG_ROOTPATH "/opt/nfsroot"
#define CONFIG_BOOTFILE "uImage"
-#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server */
+#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
#define CONFIG_LOADADDR 1000000 /* default location for tftp, bootm */
#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
#define CONFIG_BAUDRATE 115200
#define __USB_PHY_TYPE utmi
#ifdef CONFIG_PPC_T1024
-#define CONFIG_BOARDNAME "t1024rdb"
+#define CONFIG_BOARDNAME t1024rdb
+#define BANK_INTLV cs0_cs1
#else
-#define CONFIG_BOARDNAME "t1023rdb"
+#define CONFIG_BOARDNAME t1023rdb
+#define BANK_INTLV null
#endif
#define CONFIG_EXTRA_ENV_SETTINGS \
"hwconfig=fsl_ddr:ctlr_intlv=cacheline," \
- "bank_intlv=cs0_cs1\0" \
+ "bank_intlv=" __stringify(BANK_INTLV) "\0" \
"usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0" \
"ramdiskfile=" __stringify(CONFIG_BOARDNAME) "/ramdisk.uboot\0" \
"fdtfile=" __stringify(CONFIG_BOARDNAME) "/" \
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