8xxx: Change all 8*xx_DDR addresses to 8xxx

There were a number of shared files that were using
CONFIG_SYS_MPC85xx_DDR_ADDR, or CONFIG_SYS_MPC86xx_DDR_ADDR, and
several variants (DDR2, DDR3). A recent patchset added
85xx-specific ones to code which was used by 86xx systems.
After reviewing places where these constants were used, and
noting that the type definitions of the pointers assigned to
point to those addresses were the same, the cleanest approach
to fixing this problem was to unify the namespace for the
85xx, 83xx, and 86xx DDR address definitions.

This patch does:

s/CONFIG_SYS_MPC8.xx_DDR/CONFIG_SYS_MPC8xxx_DDR/g

All 85xx, 86xx, and 83xx have been built with this change.

Signed-off-by: Andy Fleming <afleming@freescale.com>
Tested-by: Andy Fleming <afleming@freescale.com>
Acked-by: Kim Phillips <kim.phillips@freescale.com>

diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c
index 78486aab85df1de371d7d0c2f29060c5b70ff44b..9b9832cfc3363b71d53893f85a7e90b8fbd46895 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/cpu.c
+++ b/arch/powerpc/cpu/mpc85xx/cpu.c
@@ -451,21 +451,21 @@ static void dump_spd_ddr_reg(void)
        for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
                switch (i) {
                case 0:
-                       ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR;
+                       ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
                        break;
-#if defined(CONFIG_SYS_MPC85xx_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
+#if defined(CONFIG_SYS_MPC8xxx_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
                case 1:
-                       ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR2_ADDR;
+                       ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR2_ADDR;
                        break;
 #endif
-#if defined(CONFIG_SYS_MPC85xx_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
+#if defined(CONFIG_SYS_MPC8xxx_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
                case 2:
-                       ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR3_ADDR;
+                       ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR3_ADDR;
                        break;
 #endif
-#if defined(CONFIG_SYS_MPC85xx_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
+#if defined(CONFIG_SYS_MPC8xxx_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
                case 3:
-                       ddr[i] = (void *)CONFIG_SYS_MPC85xx_DDR4_ADDR;
+                       ddr[i] = (void *)CONFIG_SYS_MPC8xxx_DDR4_ADDR;
                        break;
 #endif
                default:

diff --git a/arch/powerpc/cpu/mpc85xx/ddr-gen1.c b/arch/powerpc/cpu/mpc85xx/ddr-gen1.c
index 54437dd0cbd3e5b7ff5978738ba239fb1b6c2979..8a86819fb52ab0010cd1975af4e36328fada5761 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/ddr-gen1.c
+++ b/arch/powerpc/cpu/mpc85xx/ddr-gen1.c
@@ -18,7 +18,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
                             unsigned int ctrl_num)
 {
        unsigned int i;
-       volatile ccsr_ddr_t *ddr = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR;
+       volatile ccsr_ddr_t *ddr = (void *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
 
        if (ctrl_num != 0) {
                printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
@@ -73,7 +73,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 void
 ddr_enable_ecc(unsigned int dram_size)
 {
-       volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
+       volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC8xxx_DDR_ADDR);
 
        dma_meminit(CONFIG_MEM_INIT_VALUE, dram_size);
 

diff --git a/arch/powerpc/cpu/mpc85xx/ddr-gen2.c b/arch/powerpc/cpu/mpc85xx/ddr-gen2.c
index 49000a19e832f2ad9d72080f91e1bc8c0de8f54d..a7058625227bdcaa333731b8c5785b779c0299e2 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/ddr-gen2.c
+++ b/arch/powerpc/cpu/mpc85xx/ddr-gen2.c
@@ -19,14 +19,11 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
                             unsigned int ctrl_num)
 {
        unsigned int i;
-#ifdef CONFIG_MPC83xx
-       ccsr_ddr_t *ddr = (void *)CONFIG_SYS_MPC83xx_DDR_ADDR;
-#else
-       ccsr_ddr_t *ddr = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR;
-#ifdef CONFIG_SYS_FSL_ERRATUM_NMG_DDR120
+       ccsr_ddr_t *ddr = (void *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
+
+#if defined(CONFIG_SYS_FSL_ERRATUM_NMG_DDR120) && defined(CONFIG_MPC85xx)
        ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
        uint svr;
-#endif
 #endif
 
        if (ctrl_num) {

diff --git a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c
index f118dd5daf0a08e3fc3994951844217457cc6db7..ef0dd1da64ccb5a2f0e211dfbbd5000747b8a1b4 100644 (file)
--- a/arch/powerpc/cpu/mpc85xx/ddr-gen3.c
+++ b/arch/powerpc/cpu/mpc85xx/ddr-gen3.c
@@ -32,21 +32,21 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 
        switch (ctrl_num) {
        case 0:
-               ddr = (void *)CONFIG_SYS_MPC85xx_DDR_ADDR;
+               ddr = (void *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
                break;
-#if defined(CONFIG_SYS_MPC85xx_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
+#if defined(CONFIG_SYS_MPC8xxx_DDR2_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 1)
        case 1:
-               ddr = (void *)CONFIG_SYS_MPC85xx_DDR2_ADDR;
+               ddr = (void *)CONFIG_SYS_MPC8xxx_DDR2_ADDR;
                break;
 #endif
-#if defined(CONFIG_SYS_MPC85xx_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
+#if defined(CONFIG_SYS_MPC8xxx_DDR3_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 2)
        case 2:
-               ddr = (void *)CONFIG_SYS_MPC85xx_DDR3_ADDR;
+               ddr = (void *)CONFIG_SYS_MPC8xxx_DDR3_ADDR;
                break;
 #endif
-#if defined(CONFIG_SYS_MPC85xx_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
+#if defined(CONFIG_SYS_MPC8xxx_DDR4_ADDR) && (CONFIG_NUM_DDR_CONTROLLERS > 3)
        case 3:
-               ddr = (void *)CONFIG_SYS_MPC85xx_DDR4_ADDR;
+               ddr = (void *)CONFIG_SYS_MPC8xxx_DDR4_ADDR;
                break;
 #endif
        default:

diff --git a/arch/powerpc/cpu/mpc86xx/ddr-8641.c b/arch/powerpc/cpu/mpc86xx/ddr-8641.c
index b8f2c9387f591ba70d54f825e7f14763c21d01db..92ba26dc8ea1708b5d9842b42ef2a36854360121 100644 (file)
--- a/arch/powerpc/cpu/mpc86xx/ddr-8641.c
+++ b/arch/powerpc/cpu/mpc86xx/ddr-8641.c
@@ -22,10 +22,10 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
 
        switch (ctrl_num) {
        case 0:
-               ddr = (void *)CONFIG_SYS_MPC86xx_DDR_ADDR;
+               ddr = (void *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
                break;
        case 1:
-               ddr = (void *)CONFIG_SYS_MPC86xx_DDR2_ADDR;
+               ddr = (void *)CONFIG_SYS_MPC8xxx_DDR2_ADDR;
                break;
        default:
                printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);

diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
index 088cc0e855074e1b3fc74e0b6072626082e8cccb..8016bcdc22ec8b54a12ef1d7f7cf7bf4aa0d5f27 100644 (file)
--- a/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/ctrl_regs.c
@@ -18,15 +18,7 @@
 
 #include "ddr.h"
 
-#ifdef CONFIG_MPC83xx
-       #define _DDR_ADDR CONFIG_SYS_MPC83xx_DDR_ADDR
-#elif defined(CONFIG_MPC85xx)
-       #define _DDR_ADDR CONFIG_SYS_MPC85xx_DDR_ADDR
-#elif defined(CONFIG_MPC86xx)
-       #define _DDR_ADDR CONFIG_SYS_MPC86xx_DDR_ADDR
-#else
-       #error "Undefined _DDR_ADDR"
-#endif
+#define _DDR_ADDR CONFIG_SYS_MPC8xxx_DDR_ADDR
 
 static u32 fsl_ddr_get_version(void)
 {

diff --git a/arch/powerpc/cpu/mpc8xxx/ddr/util.c b/arch/powerpc/cpu/mpc8xxx/ddr/util.c
index 940ffff773a20f40ee6f2850b709bdf00acf8ad1..acfe1f095fe4c541c3b2126211c2b7ae580658dc 100644 (file)
--- a/arch/powerpc/cpu/mpc8xxx/ddr/util.c
+++ b/arch/powerpc/cpu/mpc8xxx/ddr/util.c
@@ -133,14 +133,8 @@ u32 fsl_ddr_get_intl3r(void)
 
 void board_add_ram_info(int use_default)
 {
-#if defined(CONFIG_MPC83xx)
-       immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
-       ccsr_ddr_t *ddr = (void *)&immap->ddr;
-#elif defined(CONFIG_MPC85xx)
-       ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
-#elif defined(CONFIG_MPC86xx)
-       ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC86xx_DDR_ADDR);
-#endif
+       ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC8xxx_DDR_ADDR);
+
 #if    defined(CONFIG_E6500) && (CONFIG_NUM_DDR_CONTROLLERS == 3)
        u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004);
 #endif
@@ -152,13 +146,13 @@ void board_add_ram_info(int use_default)
 
 #if CONFIG_NUM_DDR_CONTROLLERS >= 2
        if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) {
-               ddr = (void __iomem *)CONFIG_SYS_MPC85xx_DDR2_ADDR;
+               ddr = (void __iomem *)CONFIG_SYS_MPC8xxx_DDR2_ADDR;
                sdram_cfg = in_be32(&ddr->sdram_cfg);
        }
 #endif
 #if CONFIG_NUM_DDR_CONTROLLERS >= 3
        if (!(sdram_cfg & SDRAM_CFG_MEM_EN)) {
-               ddr = (void __iomem *)CONFIG_SYS_MPC85xx_DDR3_ADDR;
+               ddr = (void __iomem *)CONFIG_SYS_MPC8xxx_DDR3_ADDR;
                sdram_cfg = in_be32(&ddr->sdram_cfg);
        }
 #endif

diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h
index 679832cd6c774397161d185cedce0b4f365d85b5..8ac13fc05c08d19f25ca8b77abf261ebfb7a4b82 100644 (file)
--- a/arch/powerpc/include/asm/immap_83xx.h
+++ b/arch/powerpc/include/asm/immap_83xx.h
@@ -1035,9 +1035,9 @@ typedef struct immap {
 } immap_t;
 #endif
 
-#define CONFIG_SYS_MPC83xx_DDR_OFFSET  (0x2000)
-#define CONFIG_SYS_MPC83xx_DDR_ADDR \
-                       (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_DDR_OFFSET)
+#define CONFIG_SYS_MPC8xxx_DDR_OFFSET  (0x2000)
+#define CONFIG_SYS_MPC8xxx_DDR_ADDR \
+                       (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET)
 #define CONFIG_SYS_MPC83xx_DMA_OFFSET  (0x8000)
 #define CONFIG_SYS_MPC83xx_DMA_ADDR \
                        (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_DMA_OFFSET)

diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h
index 969f726c36296f8b749da050538fa0f357bb88d7..54aa71b92bb0cc5dd9c6d31ff906497dbaec4e13 100644 (file)
--- a/arch/powerpc/include/asm/immap_85xx.h
+++ b/arch/powerpc/include/asm/immap_85xx.h
@@ -2867,9 +2867,9 @@ struct ccsr_pman {
 #define CONFIG_SYS_FSL_CORENET_PMAN2_OFFSET    0x5000
 #define CONFIG_SYS_FSL_CORENET_PMAN3_OFFSET    0x6000
 #endif
-#define CONFIG_SYS_MPC85xx_DDR_OFFSET          0x8000
-#define CONFIG_SYS_MPC85xx_DDR2_OFFSET         0x9000
-#define CONFIG_SYS_MPC85xx_DDR3_OFFSET         0xA000
+#define CONFIG_SYS_MPC8xxx_DDR_OFFSET          0x8000
+#define CONFIG_SYS_MPC8xxx_DDR2_OFFSET         0x9000
+#define CONFIG_SYS_MPC8xxx_DDR3_OFFSET         0xA000
 #define CONFIG_SYS_FSL_CORENET_CLK_OFFSET      0xE1000
 #define CONFIG_SYS_FSL_CORENET_RCPM_OFFSET     0xE2000
 #define CONFIG_SYS_FSL_CORENET_SERDES_OFFSET   0xEA000
@@ -2929,9 +2929,9 @@ struct ccsr_pman {
 #define CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET     0xC20000
 #else
 #define CONFIG_SYS_MPC85xx_ECM_OFFSET          0x0000
-#define CONFIG_SYS_MPC85xx_DDR_OFFSET          0x2000
+#define CONFIG_SYS_MPC8xxx_DDR_OFFSET          0x2000
 #define CONFIG_SYS_MPC85xx_LBC_OFFSET          0x5000
-#define CONFIG_SYS_MPC85xx_DDR2_OFFSET         0x6000
+#define CONFIG_SYS_MPC8xxx_DDR2_OFFSET         0x6000
 #define CONFIG_SYS_MPC85xx_ESPI_OFFSET         0x7000
 #define CONFIG_SYS_MPC85xx_PCI1_OFFSET         0x8000
 #define CONFIG_SYS_MPC85xx_PCIX_OFFSET         0x8000
@@ -2998,12 +2998,12 @@ struct ccsr_pman {
        (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RCPM_OFFSET)
 #define CONFIG_SYS_MPC85xx_ECM_ADDR \
        (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ECM_OFFSET)
-#define CONFIG_SYS_MPC85xx_DDR_ADDR \
-       (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR_OFFSET)
-#define CONFIG_SYS_MPC85xx_DDR2_ADDR \
-       (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR2_OFFSET)
-#define CONFIG_SYS_MPC85xx_DDR3_ADDR \
-       (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DDR3_OFFSET)
+#define CONFIG_SYS_MPC8xxx_DDR_ADDR \
+       (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET)
+#define CONFIG_SYS_MPC8xxx_DDR2_ADDR \
+       (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR2_OFFSET)
+#define CONFIG_SYS_MPC8xxx_DDR3_ADDR \
+       (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR3_OFFSET)
 #define CONFIG_SYS_LBC_ADDR \
        (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET)
 #define CONFIG_SYS_IFC_ADDR \

diff --git a/arch/powerpc/include/asm/immap_86xx.h b/arch/powerpc/include/asm/immap_86xx.h
index cc338e4739f45a4602219b4bf51c22b830c15f28..2a704fe6b7be430349aec7daef3ecafd5e6d26ee 100644 (file)
--- a/arch/powerpc/include/asm/immap_86xx.h
+++ b/arch/powerpc/include/asm/immap_86xx.h
@@ -1252,10 +1252,10 @@ typedef struct immap {
 
 extern immap_t  *immr;
 
-#define CONFIG_SYS_MPC86xx_DDR_OFFSET  0x2000
-#define CONFIG_SYS_MPC86xx_DDR_ADDR    (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_DDR_OFFSET)
-#define CONFIG_SYS_MPC86xx_DDR2_OFFSET 0x6000
-#define CONFIG_SYS_MPC86xx_DDR2_ADDR   (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_DDR2_OFFSET)
+#define CONFIG_SYS_MPC8xxx_DDR_OFFSET  0x2000
+#define CONFIG_SYS_MPC8xxx_DDR_ADDR    (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET)
+#define CONFIG_SYS_MPC8xxx_DDR2_OFFSET 0x6000
+#define CONFIG_SYS_MPC8xxx_DDR2_ADDR   (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR2_OFFSET)
 #define CONFIG_SYS_MPC86xx_DMA_OFFSET  0x21000
 #define CONFIG_SYS_MPC86xx_DMA_ADDR    (CONFIG_SYS_IMMR + CONFIG_SYS_MPC86xx_DMA_OFFSET)
 #define CONFIG_SYS_MPC86xx_PIC_OFFSET  0x40000

diff --git a/board/exmeritus/hww1u1a/hww1u1a.c b/board/exmeritus/hww1u1a/hww1u1a.c
index 52c22faaa02551b5daddfdd1f0669f451d2cf8b1..89cfaad91f4306c60325bd34faba81c4d0a492a8 100644 (file)
--- a/board/exmeritus/hww1u1a/hww1u1a.c
+++ b/board/exmeritus/hww1u1a/hww1u1a.c
@@ -105,7 +105,7 @@ int checkboard(void)
         * and delay a while before we continue.
         */
        if (mpc85xx_gpio_get(GPIO_RESETS)) {
-               ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
+               ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
 
                puts("Debugger detected... extra device reset enabled!\n");
 

diff --git a/board/freescale/mpc8540ads/mpc8540ads.c b/board/freescale/mpc8540ads/mpc8540ads.c
index a275d3a074d8fb4fb4b490c8ec7333a06cfb2a73..418c06b655cacaec5961435189b3ae541d1febe0 100644 (file)
--- a/board/freescale/mpc8540ads/mpc8540ads.c
+++ b/board/freescale/mpc8540ads/mpc8540ads.c
@@ -184,7 +184,7 @@ void lbc_sdram_init(void)
 phys_size_t fixed_sdram(void)
 {
   #ifndef CONFIG_SYS_RAMBOOT
-       volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
+       volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC8xxx_DDR_ADDR);
 
        ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
        ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;

diff --git a/board/freescale/mpc8560ads/mpc8560ads.c b/board/freescale/mpc8560ads/mpc8560ads.c
index 285edbce6b46b7206b0b045eb55a88b4675aff30..a4f48bb23432200aeb032ad7f0d81ff1ec407da2 100644 (file)
--- a/board/freescale/mpc8560ads/mpc8560ads.c
+++ b/board/freescale/mpc8560ads/mpc8560ads.c
@@ -389,7 +389,7 @@ void lbc_sdram_init(void)
 phys_size_t fixed_sdram(void)
 {
   #ifndef CONFIG_SYS_RAMBOOT
-       volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
+       volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC8xxx_DDR_ADDR);
 
        ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
        ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;

diff --git a/board/freescale/mpc8569mds/mpc8569mds.c b/board/freescale/mpc8569mds/mpc8569mds.c
index d119c6517f65c7bbdb1f082db3f52ee1aacc5893..0d3b4186251982b8560642f13f80b2f48e023bfa 100644 (file)
--- a/board/freescale/mpc8569mds/mpc8569mds.c
+++ b/board/freescale/mpc8569mds/mpc8569mds.c
@@ -247,7 +247,7 @@ int checkboard (void)
 #if !defined(CONFIG_SPD_EEPROM)
 phys_size_t fixed_sdram(void)
 {
-       volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
+       volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
        uint d_init;
 
        out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS);

diff --git a/board/freescale/p1023rds/p1023rds.c b/board/freescale/p1023rds/p1023rds.c
index eb11f3fe12af036d3a4c71c14a30d56eb4ed9f4f..9110767a141341e1336f8f3ecb6e3c0ceccf8a4b 100644 (file)
--- a/board/freescale/p1023rds/p1023rds.c
+++ b/board/freescale/p1023rds/p1023rds.c
@@ -74,7 +74,7 @@ int checkboard(void)
 phys_size_t fixed_sdram(void)
 {
 #ifndef CONFIG_SYS_RAMBOOT
-       ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
+       ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
 
        set_next_law(0, LAW_SIZE_2G, LAW_TRGT_IF_DDR_1);
 

diff --git a/board/freescale/p1_p2_rdb_pc/spl_minimal.c b/board/freescale/p1_p2_rdb_pc/spl_minimal.c
index d48fb013b2cc40892ee76d92369e01e246f94bdd..09019e98af2118181507973e3d0c852448cf5b3a 100644 (file)
--- a/board/freescale/p1_p2_rdb_pc/spl_minimal.c
+++ b/board/freescale/p1_p2_rdb_pc/spl_minimal.c
@@ -36,7 +36,7 @@ DECLARE_GLOBAL_DATA_PTR;
  */
 static void sdram_init(void)
 {
-       ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
+       ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
 
        __raw_writel(CONFIG_SYS_DDR_CS0_BNDS, &ddr->cs0_bnds);
        __raw_writel(CONFIG_SYS_DDR_CS0_CONFIG, &ddr->cs0_config);

diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c
index 3188f59e4b670752356a37ecd60e24ebbdfd5c3a..d4a445108ad8eb55a9f1b9668676f0645dcb4065 100644 (file)
--- a/board/freescale/p2020ds/p2020ds.c
+++ b/board/freescale/p2020ds/p2020ds.c
@@ -84,7 +84,7 @@ int checkboard(void)
 
 phys_size_t fixed_sdram(void)
 {
-       volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
+       volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
        uint d_init;
 
        ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;

diff --git a/board/sbc8548/ddr.c b/board/sbc8548/ddr.c
index 45ec485c50b88a48a2bebdea1b80ff47508e8248..95085611336af8d32c5940306bcd6d40958fe9d6 100644 (file)
--- a/board/sbc8548/ddr.c
+++ b/board/sbc8548/ddr.c
@@ -91,7 +91,7 @@ void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
  */
 phys_size_t fixed_sdram(void)
 {
-       volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
+       volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC8xxx_DDR_ADDR);
 
        out_be32(&ddr->cs0_bnds,        0x0000007f);
        out_be32(&ddr->cs1_bnds,        0x008000ff);

diff --git a/board/socrates/sdram.c b/board/socrates/sdram.c
index c8235f4a9b4a29dd384dc8c8cf677ab879d27793..8a9ce790f147e36adb634d60eebae9c31b0140ad 100644 (file)
--- a/board/socrates/sdram.c
+++ b/board/socrates/sdram.c
@@ -41,7 +41,7 @@
  */
 phys_size_t fixed_sdram(void)
 {
-       volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
+       volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC8xxx_DDR_ADDR);
 
        /*
         * Disable memory controller.

diff --git a/nand_spl/board/freescale/p1010rdb/nand_boot.c b/nand_spl/board/freescale/p1010rdb/nand_boot.c
index 9c356901b13f60ba0ba90b5c580cfb4196c2f8a4..3c7bc2bc6536d55c2725a522346e3ae0f3d444b1 100644 (file)
--- a/nand_spl/board/freescale/p1010rdb/nand_boot.c
+++ b/nand_spl/board/freescale/p1010rdb/nand_boot.c
@@ -35,7 +35,7 @@ unsigned long ddr_freq_mhz;
 
 void sdram_init(void)
 {
-       ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
+       ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
        /* mask off E bit */
        u32 svr = SVR_SOC_VER(mfspr(SPRN_SVR));
 

diff --git a/nand_spl/board/freescale/p1023rds/nand_boot.c b/nand_spl/board/freescale/p1023rds/nand_boot.c
index 89e339d51207462533ee1d235b9e5b5dbdd15ed7..d6756fbf806773f37e9d44367be7f24fadea035a 100644 (file)
--- a/nand_spl/board/freescale/p1023rds/nand_boot.c
+++ b/nand_spl/board/freescale/p1023rds/nand_boot.c
@@ -33,7 +33,7 @@ DECLARE_GLOBAL_DATA_PTR;
 /* Fixed sdram init -- doesn't use serial presence detect. */
 void sdram_init(void)
 {
-       ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
+       ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC8xxx_DDR_ADDR;
 
        set_next_law(0, LAW_SIZE_2G, LAW_TRGT_IF_DDR_1);