bool "Renesas AP-325RXA"
select CPU_SH4
-config TARGET_ECOVEC
- bool "EcoVec"
- select CPU_SH4A
-
config TARGET_MIGOR
bool "Migo-R"
select CPU_SH4
source "board/ms7750se/Kconfig"
source "board/renesas/MigoR/Kconfig"
source "board/renesas/ap325rxa/Kconfig"
-source "board/renesas/ecovec/Kconfig"
source "board/renesas/r0p7734/Kconfig"
source "board/renesas/r2dplus/Kconfig"
source "board/renesas/r7780mp/Kconfig"
+++ /dev/null
-if TARGET_ECOVEC
-
-config SYS_BOARD
- default "ecovec"
-
-config SYS_VENDOR
- default "renesas"
-
-config SYS_CONFIG_NAME
- default "ecovec"
-
-endif
+++ /dev/null
-ECOVEC BOARD
-M: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com>
-M: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
-S: Maintained
-F: board/renesas/ecovec/
-F: include/configs/ecovec.h
-F: configs/ecovec_defconfig
+++ /dev/null
-# SPDX-License-Identifier: GPL-2.0+
-#
-# Copyright (C) 2011 Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
-# Copyright (C) 2011 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
-#
-
-obj-y := ecovec.o
-extra-y += lowlevel_init.o
+++ /dev/null
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copyright (C) 2009, 2011 Renesas Solutions Corp.
- * Copyright (C) 2009 Kuninori Morimoto <morimoto.kuninori@renesas.com>
- * Copyright (C) 2011 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/io.h>
-#include <asm/processor.h>
-#include <i2c.h>
-#include <netdev.h>
-
-/* USB power management register */
-#define UPONCR0 0xA40501D4
-
-int checkboard(void)
-{
- puts("BOARD: ecovec\n");
- return 0;
-}
-
-static void debug_led(u8 led)
-{
- /* PDGR[0-4] is debug LED */
- outb((inb(PGDR) & ~0x0F) | (led & 0x0F), PGDR);
-}
-
-int board_late_init(void)
-{
- u8 mac[6];
- char env_mac[18];
-
- udelay(1000);
-
- /* SH-Eth (PLCR, PNCR, PXCR, PSELx )*/
- outw(inw(PLCR) & ~0xFFF0, PLCR);
- outw(inw(PNCR) & ~0x000F, PNCR);
- outw(inw(PXCR) & ~0x0FC0, PXCR);
- outw((inw(PSELB) & ~0x030F) | 0x020A, PSELB);
- outw((inw(PSELC) & ~0x0307) | 0x0207, PSELC);
- outw((inw(PSELE) & ~0x00c0) | 0x0080, PSELE);
-
- debug_led(1 << 3);
-
- outl(inl(MSTPCR2) & ~0x10000000, MSTPCR2);
-
- i2c_set_bus_num(1); /* Use I2C 1 */
-
- /* Read MAC address */
- i2c_read(0x50, 0x10, 0, mac, 6);
-
- /* Set MAC address */
- sprintf(env_mac, "%02X:%02X:%02X:%02X:%02X:%02X",
- mac[0], mac[1], mac[2], mac[3], mac[4], mac[5]);
- env_set("ethaddr", env_mac);
-
- debug_led(0x0F);
-
- return 0;
-}
-
-int board_init(void)
-{
-
- /* LED (PTG) */
- outw((inw(PGCR) & ~0xFF) | 0x55, PGCR);
- outw((inw(HIZCRA) & ~0x02), HIZCRA);
-
- debug_led(1 << 0);
-
- /* SCIF0 (PTF, PTM) */
- outw(inw(PFCR) & ~0x30, PFCR);
- outw(inw(PMCR) & ~0x0C, PMCR);
- outw((inw(PSELA) & ~0x40) | 0x40, PSELA);
-
- debug_led(1 << 1);
-
- /* RMII (PTA) */
- outw((inw(PACR) & ~0x0C) | 0x04, PACR);
- outb((inb(PADR) & ~0x02) | 0x02, PADR);
-
- debug_led(1 << 2);
-
- /* USB host */
- outw((inw(PBCR) & ~0x300) | 0x100, PBCR);
- outb((inb(PBDR) & ~0x10) | 0x10, PBDR);
- outl(inl(MSTPCR2) & ~0x100000, MSTPCR2);
- outw(0x0600, UPONCR0);
-
- debug_led(1 << 3);
-
- /* debug switch */
- outw((inw(PVCR) & ~0x03) | 0x02 , PVCR);
-
- return 0;
-}
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Copyright (C) 2011 Renesas Solutions Corp.
- * Copyright (C) 2011 Nobuhiro Iwamatsu <nobuhiro.Iwamatsu.yj@renesas.com>
- *
- * board/renesas/ecovec/lowlevel_init.S
- */
-
-#include <config.h>
-#include <asm/processor.h>
-#include <asm/macro.h>
-#include <configs/ecovec.h>
-
- .global lowlevel_init
-
- .text
- .align 2
-
-lowlevel_init:
-
- /* jump to CONFIG_ECOVEC_ROMIMAGE_ADDR if bit 1 of PVDR_A */
- mov.l PVDR_A, r1
- mov.l PVDR_D, r2
- mov.b @r1, r0
- tst r0, r2
- bt 1f
- mov.l JUMP_A, r1
- jmp @r1
- nop
-
-1:
- /* Disable watchdog */
- write16 RWTCSR_A, RWTCSR_D
-
- /* MMU Disable */
- write32 MMUCR_A, MMUCR_D
-
- /* Setup clocks */
- write32 PLLCR_A, PLLCR_D
- write32 FRQCRA_A, FRQCRA_D
- write32 FRQCRB_A, FRQCRB_D
-
- wait_timer TIMER_D
-
- write32 MMSELR_A, MMSELR_D
-
- /* Srtup BSC */
- write32 CMNCR_A, CMNCR_D
- write32 CS0BCR_A, CS0BCR_D
- write32 CS0WCR_A, CS0WCR_D
-
- wait_timer TIMER_D
-
- /* Setup SDRAM */
- write32 DBPDCNT0_A, DBPDCNT0_D0
- write32 DBCONF_A, DBCONF_D
- write32 DBTR0_A, DBTR0_D
- write32 DBTR1_A, DBTR1_D
- write32 DBTR2_A, DBTR2_D
- write32 DBTR3_A, DBTR3_D
- write32 DBKIND_A, DBKIND_D
- write32 DBCKECNT_A, DBCKECNT_D
-
- wait_timer TIMER_D
-
- write32 DBCMDCNT_A, DBCMDCNT_D0
- write32 DBMRCNT_A, DBMRCNT_D0
- write32 DBMRCNT_A, DBMRCNT_D1
- write32 DBMRCNT_A, DBMRCNT_D2
- write32 DBMRCNT_A, DBMRCNT_D3
- write32 DBCMDCNT_A, DBCMDCNT_D0
- write32 DBCMDCNT_A, DBCMDCNT_D1
- write32 DBCMDCNT_A, DBCMDCNT_D1
- write32 DBMRCNT_A, DBMRCNT_D4
- write32 DBMRCNT_A, DBMRCNT_D5
- write32 DBMRCNT_A, DBMRCNT_D6
-
- wait_timer TIMER_D
-
- write32 DBEN_A, DBEN_D
- write32 DBRFPDN1_A, DBRFPDN1_D
- write32 DBRFPDN2_A, DBRFPDN2_D
- write32 DBCMDCNT_A, DBCMDCNT_D0
-
-
- /* Dummy read */
- mov.l DUMMY_A ,r1
- synco
- mov.l @r1, r0
- synco
-
- mov.l SDRAM_A ,r1
- synco
- mov.l @r1, r0
- synco
- wait_timer TIMER_D
-
- add #4, r1
- synco
- mov.l @r1, r0
- synco
- wait_timer TIMER_D
-
- add #4, r1
- synco
- mov.l @r1, r0
- synco
- wait_timer TIMER_D
-
- add #4, r1
- synco
- mov.l @r1, r0
- synco
- wait_timer TIMER_D
-
- write32 DBCMDCNT_A, DBCMDCNT_D0
- write32 DBCMDCNT_A, DBCMDCNT_D1
- write32 DBPDCNT0_A, DBPDCNT0_D1
- write32 DBRFPDN0_A, DBRFPDN0_D
-
- wait_timer TIMER_D
-
- write32 CCR_A, CCR_D
-
- stc sr, r0
- mov.l SR_MASK_D, r1
- and r1, r0
- ldc r0, sr
-
- rts
-
- .align 2
-
-PVDR_A: .long PVDR
-PVDR_D: .long 0x00000001
-JUMP_A: .long CONFIG_ECOVEC_ROMIMAGE_ADDR
-TIMER_D: .long 64
-RWTCSR_A: .long RWTCSR
-RWTCSR_D: .long 0x0000A507
-MMUCR_A: .long MMUCR
-MMUCR_D: .long 0x00000004
-PLLCR_A: .long PLLCR
-PLLCR_D: .long 0x00004000
-FRQCRA_A: .long FRQCRA
-FRQCRA_D: .long 0x8E003508
-FRQCRB_A: .long FRQCRB
-FRQCRB_D: .long 0x0
-MMSELR_A: .long MMSELR
-MMSELR_D: .long 0xA5A50000
-CMNCR_A: .long CMNCR
-CMNCR_D: .long 0x00000013
-CS0BCR_A: .long CS0BCR
-CS0BCR_D: .long 0x11110400
-CS0WCR_A: .long CS0WCR
-CS0WCR_D: .long 0x00000440
-DBPDCNT0_A: .long DBPDCNT0
-DBPDCNT0_D0: .long 0x00000181
-DBPDCNT0_D1: .long 0x00000080
-DBCONF_A: .long DBCONF
-DBCONF_D: .long 0x015B0002
-DBTR0_A: .long DBTR0
-DBTR0_D: .long 0x03061502
-DBTR1_A: .long DBTR1
-DBTR1_D: .long 0x02020102
-DBTR2_A: .long DBTR2
-DBTR2_D: .long 0x01090305
-DBTR3_A: .long DBTR3
-DBTR3_D: .long 0x00000002
-DBKIND_A: .long DBKIND
-DBKIND_D: .long 0x00000005
-DBCKECNT_A: .long DBCKECNT
-DBCKECNT_D: .long 0x00000001
-DBCMDCNT_A: .long DBCMDCNT
-DBCMDCNT_D0:.long 0x2
-DBCMDCNT_D1:.long 0x4
-DBMRCNT_A: .long DBMRCNT
-DBMRCNT_D0: .long 0x00020000
-DBMRCNT_D1: .long 0x00030000
-DBMRCNT_D2: .long 0x00010040
-DBMRCNT_D3: .long 0x00000532
-DBMRCNT_D4: .long 0x00000432
-DBMRCNT_D5: .long 0x000103C0
-DBMRCNT_D6: .long 0x00010040
-DBEN_A: .long DBEN
-DBEN_D: .long 0x01
-DBRFPDN0_A: .long DBRFPDN0
-DBRFPDN1_A: .long DBRFPDN1
-DBRFPDN2_A: .long DBRFPDN2
-DBRFPDN0_D: .long 0x00010000
-DBRFPDN1_D: .long 0x00000613
-DBRFPDN2_D: .long 0x238C003A
-SDRAM_A: .long 0xa8000000
-DUMMY_A: .long 0x0c400000
-CCR_A: .long CCR
-CCR_D: .long 0x0000090B
-SR_MASK_D: .long 0xEFFFFF0F
+++ /dev/null
-CONFIG_SH=y
-CONFIG_SYS_TEXT_BASE=0x8FFC0000
-CONFIG_TARGET_ECOVEC=y
-CONFIG_BOOTDELAY=3
-CONFIG_USE_BOOTARGS=y
-CONFIG_BOOTARGS="console=ttySC0,115200"
-CONFIG_VERSION_VARIABLE=y
-# CONFIG_CMDLINE_EDITING is not set
-# CONFIG_AUTO_COMPLETE is not set
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_CONSOLE is not set
-# CONFIG_CMD_BOOTD is not set
-# CONFIG_CMD_RUN is not set
-# CONFIG_CMD_IMI is not set
-# CONFIG_CMD_XIMG is not set
-# CONFIG_CMD_EDITENV is not set
-# CONFIG_CMD_ENV_EXISTS is not set
-CONFIG_CMD_I2C=y
-# CONFIG_CMD_LOADB is not set
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_SDRAM=y
-CONFIG_CMD_USB=y
-# CONFIG_CMD_ECHO is not set
-# CONFIG_CMD_ITEST is not set
-# CONFIG_CMD_SOURCE is not set
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_CMD_MII=y
-CONFIG_CMD_PING=y
-# CONFIG_CMD_MISC is not set
-CONFIG_CMD_EXT2=y
-CONFIG_CMD_FAT=y
-CONFIG_ENV_IS_IN_FLASH=y
-CONFIG_MTD_NOR_FLASH=y
-CONFIG_FLASH_CFI_DRIVER=y
-CONFIG_SYS_FLASH_CFI=y
-CONFIG_SH_ETHER=y
-CONFIG_SCIF_CONSOLE=y
-CONFIG_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_USE_PRIVATE_LIBGCC=y
+++ /dev/null
-/* SPDX-License-Identifier: GPL-2.0+ */
-/*
- * Configuation settings for the Renesas Solutions ECOVEC board
- *
- * Copyright (C) 2009 - 2011 Renesas Solutions Corp.
- * Copyright (C) 2009 Kuninori Morimoto <morimoto.kuninori@renesas.com>
- * Copyright (C) 2010, 2011 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
- */
-
-#ifndef __ECOVEC_H
-#define __ECOVEC_H
-
-/*
- * Address Interface BusWidth
- *-----------------------------------------
- * 0x0000_0000 U-Boot 16bit
- * 0x0004_0000 Linux romImage 16bit
- * 0x0014_0000 MTD for Linux 16bit
- * 0x0400_0000 Internal I/O 16/32bit
- * 0x0800_0000 DRAM 32bit
- * 0x1800_0000 MFI 16bit
- */
-
-#define CONFIG_CPU_SH7724 1
-
-#define CONFIG_ECOVEC_ROMIMAGE_ADDR 0xA0040000
-
-#define CONFIG_DISPLAY_BOARDINFO
-#undef CONFIG_SHOW_BOOT_PROGRESS
-
-/* I2C */
-#define CONFIG_SYS_I2C
-#define CONFIG_SYS_I2C_SH
-#define CONFIG_SYS_I2C_SLAVE 0x7F
-#define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 2
-#define CONFIG_SYS_I2C_SH_BASE0 0xA4470000
-#define CONFIG_SYS_I2C_SH_SPEED0 100000
-#define CONFIG_SYS_I2C_SH_BASE1 0xA4750000
-#define CONFIG_SYS_I2C_SH_SPEED1 100000
-#define CONFIG_SH_I2C_DATA_HIGH 4
-#define CONFIG_SH_I2C_DATA_LOW 5
-#define CONFIG_SH_I2C_CLOCK 41666666
-
-/* Ether */
-#define CONFIG_SH_ETHER_USE_PORT (0)
-#define CONFIG_SH_ETHER_PHY_ADDR (0x1f)
-#define CONFIG_PHY_SMSC 1
-#define CONFIG_BITBANGMII
-#define CONFIG_BITBANGMII_MULTI
-#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
-
-/* USB / R8A66597 */
-#define CONFIG_USB_R8A66597_HCD
-#define CONFIG_R8A66597_BASE_ADDR 0xA4D80000
-#define CONFIG_R8A66597_XTAL 0x0000 /* 12MHz */
-#define CONFIG_R8A66597_LDRV 0x8000 /* 3.3V */
-#define CONFIG_R8A66597_ENDIAN 0x0000 /* little */
-#define CONFIG_SUPERH_ON_CHIP_R8A66597
-
-/* undef to save memory */
-/* Monitor Command Prompt */
-/* Buffer size for Console output */
-#define CONFIG_SYS_PBSIZE 256
-/* List of legal baudrate settings for this board */
-#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
-
-/* SCIF */
-#define CONFIG_SCIF 1
-#define CONFIG_CONS_SCIF0 1
-
-/* Suppress display of console information at boot */
-
-/* SDRAM */
-#define CONFIG_SYS_SDRAM_BASE (0x88000000)
-#define CONFIG_SYS_SDRAM_SIZE (256 * 1024 * 1024)
-#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024)
-
-#define CONFIG_SYS_MEMTEST_START (CONFIG_SYS_SDRAM_BASE)
-#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 200 * 1024 * 1024)
-/* Enable alternate, more extensive, memory test */
-/* Scratch address used by the alternate memory test */
-#undef CONFIG_SYS_MEMTEST_SCRATCH
-
-/* Enable temporary baudrate change while serial download */
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE
-
-/* FLASH */
-#undef CONFIG_SYS_FLASH_QUIET_TEST
-#define CONFIG_SYS_FLASH_EMPTY_INFO
-#define CONFIG_SYS_FLASH_BASE (0xA0000000)
-#define CONFIG_SYS_MAX_FLASH_SECT 512
-
-/* if you use all NOR Flash , you change dip-switch. Please see Manual. */
-#define CONFIG_SYS_MAX_FLASH_BANKS 1
-#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
-
-/* Timeout for Flash erase operations (in ms) */
-#define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000)
-/* Timeout for Flash write operations (in ms) */
-#define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000)
-/* Timeout for Flash set sector lock bit operations (in ms) */
-#define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000)
-/* Timeout for Flash clear lock bit operations (in ms) */
-#define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000)
-
-/*
- * Use hardware flash sectors protection instead
- * of U-Boot software protection
- */
-#undef CONFIG_SYS_DIRECT_FLASH_TFTP
-
-/* Address of u-boot image in Flash (NOT run time address in SDRAM) ?!? */
-#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE)
-/* Monitor size */
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
-/* Size of DRAM reserved for malloc() use */
-#define CONFIG_SYS_MALLOC_LEN (256 * 1024)
-#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
-
-/* ENV setting */
-#define CONFIG_ENV_OVERWRITE 1
-#define CONFIG_ENV_SECT_SIZE (128 * 1024)
-#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
-#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN)
-/* Offset of env Flash sector relative to CONFIG_SYS_FLASH_BASE */
-#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE)
-#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
-
-/* Board Clock */
-#define CONFIG_SYS_CLK_FREQ 41666666
-#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
-
-#endif /* __ECOVEC_H */
CONFIG_ECC_SRAM_ADDR_MASK
CONFIG_ECC_SRAM_ADDR_SHIFT
CONFIG_ECC_SRAM_REQ_BIT
-CONFIG_ECOVEC_ROMIMAGE_ADDR
CONFIG_EDB9301
CONFIG_EDB9302
CONFIG_EDB9302A
projects / u-boot.git / commitdiff