gd->bd->bi_dsp_freq = 0;
return 0;
}
+
+unsigned long get_board_sys_clk(void)
+{
+ return clk_get(DAVINCI_ARM_CLKID);
+}
return 0;
}
-int board_postclk_init(void)
+unsigned long get_board_sys_clk(void)
{
/*
* Obtain CPU clock frequency from board and cache in global
*/
#ifdef CONFIG_SYS_FPGAREG_FREQ
- gd->cpu_clk = (*(volatile unsigned long *)CONFIG_SYS_FPGAREG_FREQ);
+ return (*(volatile unsigned long *)CONFIG_SYS_FPGAREG_FREQ);
#else
/* early Tensilica bitstreams lack this reg, but most run at 50 MHz */
- gd->cpu_clk = 50000000UL;
+ return 50000000;
#endif
+}
+
+int board_postclk_init(void)
+{
+ gd->cpu_clk = get_board_sys_clk();
+
return 0;
}
unsigned long
-get_clock_freq(void)
+get_board_sys_clk(void)
{
volatile cadmus_reg_t *cadmus = (cadmus_reg_t *)CONFIG_SYS_CADMUS_BASE_REG;
/*
* Returns either 33000000 or 66000000 as the SYS_CLK_FREQ.
*/
-extern unsigned long get_clock_freq(void);
+extern unsigned long get_board_sys_clk(void);
/*
return 0;
}
+#ifdef CONFIG_DYNAMIC_SYS_CLK_FREQ
unsigned long get_board_sys_clk(void)
{
u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
}
return 66666666;
}
+#endif
#ifdef CONFIG_DYNAMIC_DDR_CLK_FREQ
unsigned long get_board_ddr_clk(void)
#endif
}
+#ifdef CONFIG_DYNAMIC_SYS_CLK_FREQ
unsigned long get_board_sys_clk(void)
{
u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
return 66666666;
}
+#endif
#ifdef CONFIG_DYNAMIC_DDR_CLK_FREQ
unsigned long get_board_ddr_clk(void)
return 0;
}
-unsigned long get_board_sys_clk(unsigned long dummy)
+unsigned long get_board_sys_clk(void)
{
u8 sysclk_conf = CPLD_READ(sysclk_sw1);
return CONFIG_SYS_L3_SIZE;
}
-unsigned long get_board_sys_clk(void)
-{
- return CONFIG_SYS_CLK_FREQ;
-}
-
#if defined(CONFIG_SPL_MMC_BOOT)
#define GPIO1_SD_SEL 0x00020000
int board_mmc_getcd(struct mmc *mmc)
#endif
/* initialize selected port with appropriate baud rate */
- sys_clk = get_board_sys_clk();
+ sys_clk = CONFIG_SYS_CLK_FREQ;
plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
ccb_clk = sys_clk * plat_ratio / 2;
return 0;
}
-unsigned long get_board_sys_clk(void)
-{
- return CONFIG_SYS_CLK_FREQ;
-}
-
#ifdef CONFIG_TARGET_T1024RDB
void board_reset(void)
{
return CONFIG_SYS_L3_SIZE;
}
-unsigned long get_board_sys_clk(void)
-{
- return CONFIG_SYS_CLK_FREQ;
-}
-
#define FSL_CORENET_CCSR_PORSR1_RCW_MASK 0xFF800000
void board_init_f(ulong bootflag)
{
console_init_f();
/* initialize selected port with appropriate baud rate */
- sys_clk = get_board_sys_clk();
+ sys_clk = CONFIG_SYS_CLK_FREQ;
plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
uart_clk = sys_clk * plat_ratio / 2;
return CONFIG_SYS_L3_SIZE;
}
-unsigned long get_board_sys_clk(void)
-{
- return CONFIG_SYS_CLK_FREQ;
-}
-
void board_init_f(ulong bootflag)
{
u32 plat_ratio, sys_clk, ccb_clk;
console_init_f();
/* initialize selected port with appropriate baud rate */
- sys_clk = get_board_sys_clk();
+ sys_clk = CONFIG_SYS_CLK_FREQ;
plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
ccb_clk = sys_clk * plat_ratio / 2;
return 0;
}
-unsigned long get_board_sys_clk(void)
-{
- return CONFIG_SYS_CLK_FREQ;
-}
-
int misc_init_r(void)
{
u8 reg;
return CONFIG_SYS_L3_SIZE;
}
-unsigned long get_board_sys_clk(void)
-{
- return CONFIG_SYS_CLK_FREQ;
-}
-
void board_init_f(ulong bootflag)
{
u32 plat_ratio, sys_clk, ccb_clk;
console_init_f();
/* initialize selected port with appropriate baud rate */
- sys_clk = get_board_sys_clk();
+ sys_clk = CONFIG_SYS_CLK_FREQ;
plat_ratio = (in_be32(&gur->rcwsr[0]) >> 25) & 0x1f;
ccb_clk = sys_clk * plat_ratio / 2;
return (gd->bus_clk / 2);
}
-unsigned long get_board_sys_clk(unsigned long dummy)
-{
- return 66666666;
-}
-
int misc_init_f(void)
{
/* configure QRIO pis for i2c deblocking */
/*
* Return SYSCLK input frequency - 50 MHz or 66 MHz depending on POR config
*/
-unsigned long get_board_sys_clk(ulong dummy)
+unsigned long get_board_sys_clk(void)
{
#if defined(CONFIG_MPC85xx)
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
* Return DDR input clock - synchronous with SYSCLK or 66 MHz
* Note: 86xx doesn't support asynchronous DDR clk
*/
-unsigned long get_board_ddr_clk(ulong dummy)
+unsigned long get_board_ddr_clk(void)
{
volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
u32 ddr_ratio = (in_be32(&gur->porpllsr) & 0x00003e00) >> 9;
if (ddr_ratio == 0x7)
- return get_board_sys_clk(dummy);
+ return get_board_sys_clk();
#ifdef CONFIG_ARCH_P2020
if (in_be32(&gur->gpporcr) & 0x20000)
#ifndef __ASSEMBLY__
#include <linux/stringify.h>
-extern unsigned long get_clock_freq(void);
+extern unsigned long get_board_sys_clk(void);
#endif
-#define CONFIG_SYS_CLK_FREQ get_clock_freq() /* sysclk for MPC85xx */
+#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */
/*
* These can be toggled for performance analysis, otherwise use default.
#endif
#ifndef __ASSEMBLY__
-unsigned long get_board_sys_clk(unsigned long dummy);
+unsigned long get_board_sys_clk(void);
#include <linux/stringify.h>
#endif
-#define CONFIG_SYS_CLK_FREQ get_board_sys_clk(0)
+#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
/*
* These can be toggled for performance analysis, otherwise use default.
#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
#endif
-#ifndef __ASSEMBLY__
-unsigned long get_board_sys_clk(void);
-#endif
-
#define CONFIG_SYS_CLK_FREQ 100000000
/*
#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
#endif
-#ifndef __ASSEMBLY__
-unsigned long get_board_sys_clk(void);
-#endif
-
#define CONFIG_SYS_CLK_FREQ 66660000
/*
#define CONFIG_SYS_CLK_FREQ 66666666
-#ifndef __ASSEMBLY__
-unsigned long get_board_sys_clk(void);
-#endif
-
/*
* DDR Setup
*/
#define CONFIG_BITBANGMII_MULTI
/* Board Clock */
-#define RMOBILE_XTAL_CLK 20000000u
-#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
+#define CONFIG_SYS_CLK_FREQ 20000000
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootm_size=0x10000000\0" \
#endif
/* Board Clock */
-#define RMOBILE_XTAL_CLK 20000000u
-#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
+#define CONFIG_SYS_CLK_FREQ 20000000
/* ENV setting */
/* Board Clock */
/* XTAL_CLK : 33.33MHz */
-#define CONFIG_SYS_CLK_FREQ 33333333u
+#define CONFIG_SYS_CLK_FREQ 33333333
/* Generic Timer Definitions (use in assembler source) */
#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */
/*
* SoC Configuration
*/
+#ifndef __ASSEMBLY__
+unsigned long get_board_sys_clk(void);
+#endif
#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
-#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
+#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
#define CONFIG_SYS_OSCIN_FREQ 24000000
#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
/* Board Clock */
/* XTAL_CLK : 33.33MHz */
-#define CONFIG_SYS_CLK_FREQ 33333333u
+#define CONFIG_SYS_CLK_FREQ 33333333
/* Generic Timer Definitions (use in assembler source) */
#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */
/* Board Clock */
/* XTAL_CLK : 16.66MHz */
-#define CONFIG_SYS_CLK_FREQ 16666666u
+#define CONFIG_SYS_CLK_FREQ 16666666
/* Generic Timer Definitions (use in assembler source) */
#define COUNTER_FREQUENCY 0xFE502A /* 16.66MHz from CPclk */
#define CONFIG_BITBANGMII_MULTI
/* Board Clock */
-#define RMOBILE_XTAL_CLK 20000000u
-#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
+#define CONFIG_SYS_CLK_FREQ 20000000
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootm_size=0x10000000\0"
#define CONFIG_BITBANGMII_MULTI
/* Board Clock */
-#define RMOBILE_XTAL_CLK 20000000u
-#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
+#define CONFIG_SYS_CLK_FREQ 20000000
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootm_size=0x10000000\0"
#define CONFIG_BITBANGMII_MULTI
/* Board Clock */
-#define RMOBILE_XTAL_CLK 20000000u
-#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
+#define CONFIG_SYS_CLK_FREQ 20000000
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootm_size=0x10000000\0"
/*
* SoC Configuration
*/
+#ifndef __ASSEMBLY__
+unsigned long get_board_sys_clk(void);
+#endif
#define CONFIG_SYS_EXCEPTION_VECTORS_HIGH
-#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
+#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
#define CONFIG_SYS_OSCIN_FREQ 24000000
#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
/*
* SoC Configuration
*/
-#define CONFIG_SYS_CLK_FREQ clk_get(DAVINCI_ARM_CLKID)
+#ifndef __ASSEMBLY__
+unsigned long get_board_sys_clk(void);
+#endif
+#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
#define CONFIG_SYS_OSCIN_FREQ 24000000
#define CONFIG_SYS_TIMERBASE DAVINCI_TIMER0_BASE
#define CONFIG_SYS_HZ_CLOCK clk_get(DAVINCI_AUXCLK_CLKID)
#define CONFIG_BITBANGMII_MULTI
/* Board Clock */
-#define RMOBILE_XTAL_CLK 20000000u
-#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
+#define CONFIG_SYS_CLK_FREQ 20000000
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootm_size=0x10000000\0"
#define CONFIG_BITBANGMII_MULTI
/* Board Clock */
-#define RMOBILE_XTAL_CLK 20000000u
-#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
+#define CONFIG_SYS_CLK_FREQ 20000000
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootm_size=0x10000000\0"
#define CONFIG_BITBANGMII_MULTI
/* Board Clock */
-#define RMOBILE_XTAL_CLK 20000000u
-#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
+#define CONFIG_SYS_CLK_FREQ 20000000
#define CONFIG_EXTRA_ENV_SETTINGS \
"bootm_size=0x10000000\0"
#define CONFIG_XTFPGA
/* FPGA CPU freq after init */
-#define CONFIG_SYS_CLK_FREQ (gd->cpu_clk)
+#ifndef __ASSEMBLY__
+unsigned long get_board_sys_clk(void);
+#endif
+#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
/*===================*/
/* RAM Layout */
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