ARM: DRA7: emif: Check for enable bits before updating leveling output

Read and write leveling can be enabled independently. Check for these
enable bits before updating the read and write leveling output values.
This will allow to use the combination of software and hardware leveling.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Tom Rini <trini@konsulko.com>

diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c
index 6b33b45e7ccc0470f258faa01f3551b4bc940f43..36738847b12c095630c61770d9b1da6a5997ad30 100644 (file)
--- a/arch/arm/cpu/armv7/omap-common/emif-common.c
+++ b/arch/arm/cpu/armv7/omap-common/emif-common.c
@@ -250,33 +250,39 @@ static void update_hwleveling_output(u32 base, const struct emif_regs *regs)
 {
        struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
        u32 *emif_ext_phy_ctrl_reg, *emif_phy_status;
-       u32 reg, i;
+       u32 reg, i, phy;
 
        emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[7];
+       phy = readl(&emif->emif_ddr_phy_ctrl_1);
 
        /* Update PHY_REG_RDDQS_RATIO */
        emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_7;
-       for (i = 0; i < PHY_RDDQS_RATIO_REGS; i++) {
-               reg = readl(emif_phy_status++);
-               writel(reg, emif_ext_phy_ctrl_reg++);
-               writel(reg, emif_ext_phy_ctrl_reg++);
-       }
+       if (!(phy & EMIF_DDR_PHY_CTRL_1_RDLVL_MASK_MASK))
+               for (i = 0; i < PHY_RDDQS_RATIO_REGS; i++) {
+                       reg = readl(emif_phy_status++);
+                       writel(reg, emif_ext_phy_ctrl_reg++);
+                       writel(reg, emif_ext_phy_ctrl_reg++);
+               }
 
        /* Update PHY_REG_FIFO_WE_SLAVE_RATIO */
        emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_2;
-       for (i = 0; i < PHY_FIFO_WE_SLAVE_RATIO_REGS; i++) {
-               reg = readl(emif_phy_status++);
-               writel(reg, emif_ext_phy_ctrl_reg++);
-               writel(reg, emif_ext_phy_ctrl_reg++);
-       }
+       emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[12];
+       if (!(phy & EMIF_DDR_PHY_CTRL_1_RDLVLGATE_MASK_MASK))
+               for (i = 0; i < PHY_FIFO_WE_SLAVE_RATIO_REGS; i++) {
+                       reg = readl(emif_phy_status++);
+                       writel(reg, emif_ext_phy_ctrl_reg++);
+                       writel(reg, emif_ext_phy_ctrl_reg++);
+               }
 
        /* Update PHY_REG_WR_DQ/DQS_SLAVE_RATIO */
        emif_ext_phy_ctrl_reg = (u32 *)&emif->emif_ddr_ext_phy_ctrl_12;
-       for (i = 0; i < PHY_REG_WR_DQ_SLAVE_RATIO_REGS; i++) {
-               reg = readl(emif_phy_status++);
-               writel(reg, emif_ext_phy_ctrl_reg++);
-               writel(reg, emif_ext_phy_ctrl_reg++);
-       }
+       emif_phy_status = (u32 *)&emif->emif_ddr_phy_status[17];
+       if (!(phy & EMIF_DDR_PHY_CTRL_1_WRLVL_MASK_MASK))
+               for (i = 0; i < PHY_REG_WR_DQ_SLAVE_RATIO_REGS; i++) {
+                       reg = readl(emif_phy_status++);
+                       writel(reg, emif_ext_phy_ctrl_reg++);
+                       writel(reg, emif_ext_phy_ctrl_reg++);
+               }
 
        /* Disable Leveling */
        writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);

diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c
index a8d63c23c8c6df5312fbd996a108d5bd22281bab..c386e644b1fce05727b576e0e988acff561bcbc9 100644 (file)
--- a/arch/arm/cpu/armv7/omap5/sdram.c
+++ b/arch/arm/cpu/armv7/omap5/sdram.c
@@ -643,11 +643,12 @@ static void do_ext_phy_settings_dra7(u32 base, const struct emif_regs *regs)
        u32 *emif_ext_phy_ctrl_base = 0;
        u32 emif_nr;
        const u32 *ext_phy_ctrl_const_regs;
-       u32 i, hw_leveling, size;
+       u32 i, hw_leveling, size, phy;
 
        emif_nr = (base == EMIF1_BASE) ? 1 : 2;
 
        hw_leveling = regs->emif_rd_wr_lvl_rmp_ctl >> EMIF_REG_RDWRLVL_EN_SHIFT;
+       phy = regs->emif_ddr_phy_ctlr_1_init;
 
        emif_ext_phy_ctrl_base = (u32 *)&(emif->emif_ddr_ext_phy_ctrl_1);
 
@@ -657,18 +658,35 @@ static void do_ext_phy_settings_dra7(u32 base, const struct emif_regs *regs)
        writel(ext_phy_ctrl_const_regs[0], &emif_ext_phy_ctrl_base[0]);
        writel(ext_phy_ctrl_const_regs[0], &emif_ext_phy_ctrl_base[1]);
 
-       if (!hw_leveling) {
-               /*
-                * Copy the predefined PHY register values
-                * in case of sw leveling
-                */
-               for (i = 1; i < 25; i++) {
+       /*
+        * Copy the predefined PHY register values
+        * if leveling is disabled.
+        */
+       if (phy & EMIF_DDR_PHY_CTRL_1_RDLVLGATE_MASK_MASK)
+               for (i = 1; i < 6; i++) {
                        writel(ext_phy_ctrl_const_regs[i],
                               &emif_ext_phy_ctrl_base[i * 2]);
                        writel(ext_phy_ctrl_const_regs[i],
                               &emif_ext_phy_ctrl_base[i * 2 + 1]);
                }
-       } else {
+
+       if (phy & EMIF_DDR_PHY_CTRL_1_RDLVL_MASK_MASK)
+               for (i = 6; i < 11; i++) {
+                       writel(ext_phy_ctrl_const_regs[i],
+                              &emif_ext_phy_ctrl_base[i * 2]);
+                       writel(ext_phy_ctrl_const_regs[i],
+                              &emif_ext_phy_ctrl_base[i * 2 + 1]);
+               }
+
+       if (phy & EMIF_DDR_PHY_CTRL_1_WRLVL_MASK_MASK)
+               for (i = 11; i < 25; i++) {
+                       writel(ext_phy_ctrl_const_regs[i],
+                              &emif_ext_phy_ctrl_base[i * 2]);
+                       writel(ext_phy_ctrl_const_regs[i],
+                              &emif_ext_phy_ctrl_base[i * 2 + 1]);
+               }
+
+       if (hw_leveling) {
                /*
                 * Write the init value for HW levling to occur
                 */

diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h
index 7986e6e7949094d23995977f87f78c29435cf466..b03cf5a8c4ed4d6bcefe1dcee67f48d1dff7ed5d 100644 (file)
--- a/arch/arm/include/asm/emif.h
+++ b/arch/arm/include/asm/emif.h
@@ -478,6 +478,12 @@
 #define EMIF_REG_DLL_SLAVE_DLY_CTRL_SHDW_MASK  (0xFF << 4)
 #define EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHDW_SHIFT 12
 #define EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHDW_MASK    (0xFFFFF << 12)
+#define EMIF_DDR_PHY_CTRL_1_WRLVL_MASK_SHIFT           25
+#define EMIF_DDR_PHY_CTRL_1_WRLVL_MASK_MASK            (1 << 25)
+#define EMIF_DDR_PHY_CTRL_1_RDLVLGATE_MASK_SHIFT       26
+#define EMIF_DDR_PHY_CTRL_1_RDLVLGATE_MASK_MASK                (1 << 26)
+#define EMIF_DDR_PHY_CTRL_1_RDLVL_MASK_SHIFT           27
+#define EMIF_DDR_PHY_CTRL_1_RDLVL_MASK_MASK            (1 << 27)
 
 /* DDR_PHY_CTRL_2 */
 #define EMIF_REG_DDR_PHY_CTRL_2_SHIFT          0