armv8: fsl-layerscape: change tlb base from OCRAM to DDR in EL < 3

Change tlb base address from OCRAM to DDR when exception level is
less than 3.

Signed-off-by: Ruchika Gupta <ruchika.gupta@nxp.com>
Signed-off-by: Pankit Garg <pankit.garg@nxp.com>
Reviewed-by: York Sun <york.sun@nxp.com>

diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
index e01b029d64424952cce99e03052f7eaa1ab088a7..336909cfe5f296b4b7e6dd698acbf6cd67d7f039 100644 (file)
--- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
+++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c
@@ -371,7 +371,10 @@ static inline void early_mmu_setup(void)
        unsigned int el = current_el();
 
        /* global data is already setup, no allocation yet */
-       gd->arch.tlb_addr = CONFIG_SYS_FSL_OCRAM_BASE;
+       if (el == 3)
+               gd->arch.tlb_addr = CONFIG_SYS_FSL_OCRAM_BASE;
+       else
+               gd->arch.tlb_addr = CONFIG_SYS_DDR_SDRAM_BASE;
        gd->arch.tlb_fillptr = gd->arch.tlb_addr;
        gd->arch.tlb_size = EARLY_PGTABLE_SIZE;