ARM: k2g: Configure reset mux to device reset

BOOTCFG_RSTMUX8 register controls the reset mux associated with the ARM.
Timer5(dedicated to ARM) when used as WatchDog timer, the events it
generates are routed to the above mux.

Following are the 3 events that can controlled bt the reset mux:
- Device Reset
- An interrupt to the ARM_GIC
- An interrupt to the ARM_GIC followed by a device reset.

Right now to give a default watchdog behaviour "Device reset" is
being selected.

Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Acked-by: Nishanth Menon <nm@ti.com>

diff --git a/arch/arm/mach-keystone/include/mach/hardware-k2g.h b/arch/arm/mach-keystone/include/mach/hardware-k2g.h
index ca2a119d390139e4750358f874b3d35422f3a21e..0f6bf61867a6f9454ebd24b21ee680cd2c94af4d 100644 (file)
--- a/arch/arm/mach-keystone/include/mach/hardware-k2g.h
+++ b/arch/arm/mach-keystone/include/mach/hardware-k2g.h
@@ -74,4 +74,16 @@
 #define K2G_GPIO_DIR_OFFSET            0x0
 #define K2G_GPIO_SETDATA_OFFSET                0x8
 
+/* BOOTCFG RESETMUX8 */
+#define KS2_RSTMUX8                    (KS2_DEVICE_STATE_CTRL_BASE + 0x328)
+
+/* RESETMUX register definitions */
+#define RSTMUX_LOCK8_SHIFT             0x0
+#define RSTMUX_LOCK8_MASK              (0x1 << 0)
+#define RSTMUX_OMODE8_SHIFT            0x1
+#define RSTMUX_OMODE8_MASK             (0x7 << 1)
+#define RSTMUX_OMODE8_DEV_RESET                0x2
+#define RSTMUX_OMODE8_INT              0x3
+#define RSTMUX_OMODE8_INT_AND_DEV_RESET        0x4
+
 #endif /* __ASM_ARCH_HARDWARE_K2G_H */

diff --git a/board/ti/ks2_evm/board_k2g.c b/board/ti/ks2_evm/board_k2g.c
index b62c4122503905be6339f8585a5274e68152839c..8f16845d8e05f868882b2f019e522763a85403a9 100644 (file)
--- a/board/ti/ks2_evm/board_k2g.c
+++ b/board/ti/ks2_evm/board_k2g.c
@@ -117,12 +117,28 @@ int board_mmc_init(bd_t *bis)
 #endif
 
 #ifdef CONFIG_BOARD_EARLY_INIT_F
+
+static void k2g_reset_mux_config(void)
+{
+       /* Unlock the reset mux register */
+       clrbits_le32(KS2_RSTMUX8, RSTMUX_LOCK8_MASK);
+
+       /* Configure BOOTCFG_RSTMUX8 for WDT event to cause a device reset */
+       clrsetbits_le32(KS2_RSTMUX8, RSTMUX_OMODE8_MASK,
+                       RSTMUX_OMODE8_DEV_RESET << RSTMUX_OMODE8_SHIFT);
+
+       /* lock the reset mux register to prevent any spurious writes. */
+       setbits_le32(KS2_RSTMUX8, RSTMUX_LOCK8_MASK);
+}
+
 int board_early_init_f(void)
 {
        init_plls();
 
        k2g_mux_config();
 
+       k2g_reset_mux_config();
+
        /* deassert FLASH_HOLD */
        clrbits_le32(K2G_GPIO1_BANK2_BASE + K2G_GPIO_DIR_OFFSET,
                     BIT(9));