net: mvpp2.c: Enable 10G support for port 0 (SFI)

This patch fixes some remaining issues in the mvpp2 driver for the 10GB
support on port 0. These changes are:

- Incorrect PCS configuration
- Skip PHY configuration when no PHY is connected
- Skip GMAC configurations if 10G SFI mode set

Signed-off-by: Stefan Chulski <stefanc@marvell.com>
Signed-off-by: Stefan Roese <sr@denx.de>
Cc: Kostya Porotchkin <kostap@marvell.com>
Cc: Nadav Haklai <nadavh@marvell.com>
Cc: Joe Hershberger <joe.hershberger@ni.com>
Acked-by: Joe Hershberger <joe.hershberger@ni.com>

diff --git a/drivers/net/mvpp2.c b/drivers/net/mvpp2.c
index 6dc7239cd7af6e5606b03eff8047ae8d551dc729..1b46218e4dd91b3ec32928f625b32f9cb2ba6d76 100644 (file)
--- a/drivers/net/mvpp2.c
+++ b/drivers/net/mvpp2.c
@@ -442,7 +442,7 @@ do {                                                                        \
 /* MPCS registers */
 
 #define PCS40G_COMMON_CONTROL                  0x14
-#define      FORWARD_ERROR_CORRECTION_MASK     BIT(1)
+#define      FORWARD_ERROR_CORRECTION_MASK     BIT(10)
 
 #define PCS_CLOCK_RESET                                0x14c
 #define      TX_SD_CLK_RESET_MASK              BIT(0)
@@ -3251,7 +3251,7 @@ static int gop_xpcs_mode(struct mvpp2_port *port, int num_of_lanes)
 
        /* configure XG MAC mode */
        val = readl(port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG);
-       val &= ~MVPP22_XPCS_PCSMODE_OFFS;
+       val &= ~MVPP22_XPCS_PCSMODE_MASK;
        val &= ~MVPP22_XPCS_LANEACTIVE_MASK;
        val |= (2 * lane) << MVPP22_XPCS_LANEACTIVE_OFFS;
        writel(val, port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG);
@@ -4479,7 +4479,15 @@ static int mvpp2_rx_refill(struct mvpp2_port *port,
 /* Set hw internals when starting port */
 static void mvpp2_start_dev(struct mvpp2_port *port)
 {
-       mvpp2_gmac_max_rx_size_set(port);
+       switch (port->phy_interface) {
+       case PHY_INTERFACE_MODE_RGMII:
+       case PHY_INTERFACE_MODE_RGMII_ID:
+       case PHY_INTERFACE_MODE_SGMII:
+               mvpp2_gmac_max_rx_size_set(port);
+       default:
+               break;
+       }
+
        mvpp2_txp_max_tx_size_set(port);
 
        if (port->priv->hw_version == MVPP21)
@@ -4574,11 +4582,16 @@ static int mvpp2_open(struct udevice *dev, struct mvpp2_port *port)
                return err;
        }
 
-       err = mvpp2_phy_connect(dev, port);
-       if (err < 0)
-               return err;
+       if (port->phy_node) {
+               err = mvpp2_phy_connect(dev, port);
+               if (err < 0)
+                       return err;
 
-       mvpp2_link_event(port);
+               mvpp2_link_event(port);
+       } else {
+               mvpp2_egress_enable(port);
+               mvpp2_ingress_enable(port);
+       }
 
        mvpp2_start_dev(port);
 
@@ -4723,13 +4736,19 @@ static int phy_info_parse(struct udevice *dev, struct mvpp2_port *port)
        const char *phy_mode_str;
        int phy_node;
        u32 id;
-       u32 phyaddr;
+       u32 phyaddr = 0;
        int phy_mode = -1;
 
        phy_node = fdtdec_lookup_phandle(gd->fdt_blob, port_node, "phy");
-       if (phy_node < 0) {
-               dev_err(&pdev->dev, "missing phy\n");
-               return -ENODEV;
+
+       if (phy_node > 0) {
+               phyaddr = fdtdec_get_int(gd->fdt_blob, phy_node, "reg", 0);
+               if (phyaddr < 0) {
+                       dev_err(&pdev->dev, "could not find phy address\n");
+                       return -1;
+               }
+       } else {
+               phy_node = 0;
        }
 
        phy_mode_str = fdt_getprop(gd->fdt_blob, port_node, "phy-mode", NULL);
@@ -4755,8 +4774,6 @@ static int phy_info_parse(struct udevice *dev, struct mvpp2_port *port)
        port->phy_speed = fdtdec_get_int(gd->fdt_blob, port_node,
                                         "phy-speed", 1000);
 
-       phyaddr = fdtdec_get_int(gd->fdt_blob, phy_node, "reg", 0);
-
        port->id = id;
        if (port->priv->hw_version == MVPP21)
                port->first_rxq = port->id * rxq_number;
@@ -5316,7 +5333,14 @@ static int mvpp2_start(struct udevice *dev)
        /* Reconfigure parser accept the original MAC address */
        mvpp2_prs_update_mac_da(port, port->dev_addr);
 
-       mvpp2_port_power_up(port);
+       switch (port->phy_interface) {
+       case PHY_INTERFACE_MODE_RGMII:
+       case PHY_INTERFACE_MODE_RGMII_ID:
+       case PHY_INTERFACE_MODE_SGMII:
+               mvpp2_port_power_up(port);
+       default:
+               break;
+       }
 
        mvpp2_open(dev, port);
 
@@ -5479,7 +5503,8 @@ static int mvpp2_probe(struct udevice *dev)
                        port->gop_id * MVPP22_PORT_OFFSET;
 
                /* Set phy address of the port */
-               mvpp22_smi_phy_addr_cfg(port);
+               if(port->phy_node)
+                       mvpp22_smi_phy_addr_cfg(port);
 
                /* GoP Init */
                gop_port_init(port);