arm: mvebu: a38x: serdes: Update comment about PCIE*_ENABLE_* defines

These are part of SOC_CONTROL_REG1 register, not PEX_CAPABILITIES_REG.

Signed-off-by: Pali Rohár <pali@kernel.org>
Reviewed-by: Marek Behún <marek.behun@nic.cz>
Reviewed-by: Stefan Roese <sr@denx.de>

diff --git a/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h b/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h
index 55a4c267c46fb99dd9e06299d7488a89b29e5c82..64193d528886e82b6c89813109c5c50bd70476bf 100644 (file)
--- a/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h
+++ b/arch/arm/mach-mvebu/serdes/a38x/ctrl_pex.h
@@ -12,7 +12,7 @@
 /* Direct access to PEX0 Root Port's PCIe Capability structure */
 #define PEX0_RP_PCIE_CFG_OFFSET                (0x00080000 + 0x60)
 
-/* PEX_CAPABILITIES_REG fields */
+/* SOC_CONTROL_REG1 fields */
 #define PCIE0_ENABLE_OFFS              0
 #define PCIE0_ENABLE_MASK              (0x1 << PCIE0_ENABLE_OFFS)
 #define PCIE1_ENABLE_OFFS              1