{
struct sh_eth_info *port_info = ð->port_info[eth->port];
+ invalidate_cache(ADDR_TO_P2(port_info->rx_desc_cur->rd2), MAX_BUF_SIZE);
+
/* Make current descriptor available again */
if (port_info->rx_desc_cur->rd0 & RD_RDLE)
port_info->rx_desc_cur->rd0 = RD_RACT | RD_RDLE;
goto err;
}
- flush_cache_wback(port_info->tx_desc_alloc, alloc_desc_size);
-
/* Make sure we use a P2 address (non-cacheable) */
port_info->tx_desc_base =
(struct tx_desc_s *)ADDR_TO_P2((uintptr_t)port_info->tx_desc_alloc);
cur_tx_desc--;
cur_tx_desc->td0 |= TD_TDLE;
+ flush_cache_wback(port_info->tx_desc_alloc, alloc_desc_size);
/*
* Point the controller to the tx descriptor list. Must use physical
* addresses
goto err;
}
- flush_cache_wback(port_info->rx_desc_alloc, alloc_desc_size);
-
/* Make sure we use a P2 address (non-cacheable) */
port_info->rx_desc_base =
(struct rx_desc_s *)ADDR_TO_P2((uintptr_t)port_info->rx_desc_alloc);
cur_rx_desc--;
cur_rx_desc->rd0 |= RD_RDLE;
+ invalidate_cache(port_info->rx_buf_alloc, NUM_RX_DESC * MAX_BUF_SIZE);
+ flush_cache_wback(port_info->rx_desc_alloc, alloc_desc_size);
+
/* Point the controller to the rx descriptor list */
sh_eth_write(port_info, ADDR_TO_PHY(port_info->rx_desc_base), RDLAR);
#if defined(SH_ETH_TYPE_GETHER) || defined(SH_ETH_TYPE_RZ)