esdhc: Detecting 8 bit width before mmc initialization

The upper 4 data signals of esdhc are shared with spi flash.
So detect if the upper 4 pins are assigned to esdhc before
enable sdhc 8 bit width.

Signed-off-by: Haijun Zhang <haijun.zhang@freescale.com>
Acked-by: Pantelis Antoniou <panto@antoniou-consulting.com>
Reviewed-by: York Sun <yorksun@freescale.com>

diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c
index f79f167a7ddf9acc1126401467ddccb387c8356a..7b146a360444b1a3f524aaf43c0be0eac76eb0aa 100644 (file)
--- a/drivers/mmc/fsl_esdhc.c
+++ b/drivers/mmc/fsl_esdhc.c
@@ -596,6 +596,11 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg)
        if (caps & ESDHC_HOSTCAPBLT_HSS)
                mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;
 
+#ifdef CONFIG_ESDHC_DETECT_8_BIT_QUIRK
+       if (CONFIG_ESDHC_DETECT_8_BIT_QUIRK)
+               mmc->host_caps &= ~MMC_MODE_8BIT;
+#endif
+
        mmc->f_min = 400000;
        mmc->f_max = MIN(gd->arch.sdhc_clk, 52000000);
 

diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h
index 5b1ed639778a0dad91e1ade5c4f1fbedca51c2d1..0d43c27916ab1a13c12a861ccc28985a77cc67a8 100644 (file)
--- a/include/configs/T4240QDS.h
+++ b/include/configs/T4240QDS.h
@@ -167,6 +167,7 @@ unsigned long get_board_ddr_clk(void);
 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE  0x08
 #define QIXIS_BRDCFG5                  0x55
 #define QIXIS_MUX_SDHC                 2
+#define QIXIS_MUX_SDHC_WIDTH8          1
 #define QIXIS_BASE_PHYS                (0xf00000000ull | QIXIS_BASE)
 
 #define CONFIG_SYS_CSPR3_EXT   (0xf)
@@ -471,6 +472,8 @@ unsigned long get_board_ddr_clk(void);
 #define CONFIG_ESDHC_DETECT_QUIRK \
        (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC) || \
        IS_SVR_REV(get_svr(), 1, 0))
+#define CONFIG_ESDHC_DETECT_8_BIT_QUIRK \
+       (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC_WIDTH8))
 #endif
 
 #define CONFIG_BOOTDELAY       10      /* -1 disables auto-boot */