drivers/ddr/fsl: Fix workaround for A009803

Wrong field was masked in this workaround due to wrong endianness. The
impacted SoCs have big-endian.

Signed-off-by: York Sun <york.sun@nxp.com>

diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c
index b3a27ec5a86127266f30964f77fa168162b800c8..7df917841593a7a052295bedd7b1cfea6ac896aa 100644 (file)
--- a/drivers/ddr/fsl/fsl_ddr_gen4.c
+++ b/drivers/ddr/fsl/fsl_ddr_gen4.c
@@ -210,7 +210,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
        if (regs->ddr_sdram_cfg_2 & SDRAM_CFG2_AP_EN) {
                if (regs->ddr_sdram_cfg & SDRAM_CFG_RD_EN) { /* for RDIMM */
                        ddr_out32(&ddr->ddr_sdram_rcw_2,
-                                 regs->ddr_sdram_rcw_2 & ~0x0f000000);
+                                 regs->ddr_sdram_rcw_2 & ~0xf0);
                }
                ddr_out32(&ddr->err_disable, regs->err_disable |
                          DDR_ERR_DISABLE_APED);